Contents
1 Introduction
1.1 Additional Documents
1.2 Typographical Conventions
1.3 Part Identification
1.4 Glossary
1.5 Registers and Bit Fields
1.6 Disclaimer
2 Overview
2.1 eCOG1k Block Diagram
2.2 Feature List
2.3 eCOG1k Pin Diagram
2.4 eCOG1k Pin List
2.5 eCOG1k Pin Functions
2.6 CPU
2.7 Memory
2.8 Interrupts
2.9 Serial Peripherals
2.10 Timers
2.11 Port Configurator
2.12 External Host Interface
2.13 Analogue Voltage and Temperature
Sensors
2.14 eICE Debugger
2.15 Recommended Approach for This Document
3 CPU
3.1 Programmer's Model
3.2 Instruction Set
3.3 Processor Operating Modes
3.4 Flags
3.5 Instruction Formats
3.6 Instruction Timings
4 Memory Management Unit
4.1 Operation
4.2 Configuration
4.3 Memory Management Unit Registers
5 Instruction Cache
5.1 Overview
5.2 Operation
5.3 Cache Mode Selection
5.4 Cache Initialisation
5.5 Locking the Cache
5.6 Cache Writeback Bank Selection
5.7 Cache Wait States
5.8 Software Debugging with Cache
5.9 Instruction Cache Control Registers
6 Interrupts
6.1 Overview
6.2 Interrupt Handler
6.3 Interrupt Latency
6.4 Interrupt Priority
6.5 Interrupt Vectors
6.6 Timer Interrupts
6.7 DUSART Interrupts
6.8 User Serial Port Interrupts
6.9 Smart Card Interface Interrupts
6.10 IFR Interrupts
6.11 UART Interrupts
6.12 SPI Interrupts
6.13 I2C Interrupts
6.14 DUART Interrupts
6.15 External Host Interface Interrupts
7 System Support Module
7.1 System Clock Control
7.2 Sleep
7.3 Wakeup
7.4 System Reset Control
7.5 Analogue Clock and Reset Control
7.6 Reset summary
7.7 System Support Module Registers
8 Port Configurator
8.1 Configuration Rules
8.2 Low Power Considerations
8.3 Port Configurator Registers
9 Parallel I/O
9.1 Overview
9.2 Performance
9.3 Parallel I/O Registers
10 General Purpose I/O
10.1 Overview
10.2 GPIO Inputs
10.3 GPIO Outputs
10.4 GPIO Interrupts
10.5 Unused GPIO Signals
10.6 GPIO Registers
11 Timer/Counter Module
11.1 Initialisation
11.2 Interrupts
11.3 Reload
11.4 Reading the Timer Count Registers
11.5 Timer
11.6 Counter
11.7 PWM
11.8 Capture Timer
11.9 Watchdog Timer
11.10 Long Interval Timer
11.11 Timer/Counter Registers
12 DUART
12.1 Initialisation
12.2 Receive Sampling
12.3 Transmit Sampling
12.4 Baud Rates
12.5 Transmitter
12.6 Receiver
12.7 Limitations
12.8 DUART Registers
13 DUSART
13.1 Configuration
13.2 Initialisation
13.3 Receive Filter
13.4 Sample Strobe and Synchroniser
13.5 Parity Calculator
13.6 Transmit Serialiser
13.7 Protocol Control Engines
13.8 DUSART Registers
14 DUSART: I2C Serial Interface
14.1 Overview
14.2 Initialisation
14.3 Interrupts
14.4 I2C Control
14.5 I2C Master
14.6 I2C Slave
14.7 Arbitration
14.8 I2C Registers
15 DUSART: SPI Serial Interface
15.1 Overview
15.2 Clock Initialisation
15.3 Serial Clock Polarity and Phase
15.4 SPI Controller
15.5 Chip Selects
15.6 Operation
15.7 Limitations
15.8 SPI Registers
16 DUSART: UART Serial Port
16.1 Overview
16.2 Initialisation
16.3 Baud rates
16.4 UART Serial Controller
16.5 Operation
16.6 UART Registers
17 DUSART: Smart Card Interface
17.1 Overview
17.2 SCI Control Finite State Machine
17.3 SCI Delay Timer
17.4 General Information
17.5 Smart Card Interface Registers
18 DUSART: Infra-Red Interface
18.1 Overview
18.2 Initialisation
18.3 Operation
18.4 IFR Counters
18.5 IFR Datapath
18.6 Infra-Red Interface Registers
19 DUSART: User Serial Port
19.1 Overview
19.2 Initialisation
19.3 Baud Rates
19.4 Design Description
19.5 USR Additional Functions
19.6 Example Frame Transmit and Receive
Sequences
19.7 User Serial Port Registers
20 External Memory Interface (EMI)
20.1 External Signals
20.2 Bus Interface Mode
20.3 Bus Mode Connections
20.4 Bus Mode Timing Parameters
20.5 Bus Mode Timing Diagrams
20.6 Bus Interface Limitations
20.7 SDRAM Interface Mode
20.8 SDRAM Connections
20.9 SDRAM Timing Parameters
20.10 SDRAM Timing Diagrams
20.11 SDRAM Mode Limitations
20.12 Address Error Interrupt
20.13 External Memory Interface Registers
21 External Host Interface (EHI)
21.1 Memory Mapped Peripheral (MMP) Port
21.2 Direct Memory Access (DMA) Port
21.3 Access Arbitration
21.4 External Connections and Timing
21.5 External Host Interface Registers
22 Embedded Flash Memory
22.1 Overview
22.2 Reset Condition
22.3 Wait States
22.4 Programming
22.5 Flash Memory Read and Write Protect
22.6 General Purpose Information Block Words
22.7 Erase Methods
22.8 Programming Methods
22.9 Information Block Read
22.10 MMU Setup for Flash Memory Access
22.11 Operation Timings
22.12 Embedded Flash Memory Registers
23 Analogue Inputs
23.1 ADC
23.2 Analogue Multiplexer
23.3 Analogue Input Signals
23.4 Voltage Reference
23.5 Temperature sensor
23.6 Supply Voltage Sensor
23.7 Power-On Reset
23.8 Configuration
23.9 Operation
23.10 Error Conditions and Indications
23.11 ADC Operation on Early eCOG1i Devices
23.12 Analogue to Digital Converter
Registers
Appendix A Applications Information
A.1 Connections
A.2 Power Supplies and Decoupling
Appendix B Electrical Characteristics
B.1 Recommended Operating Conditions
B.2 Absolute Maximum Ratings
B.3 Supply Current
B.4 DC Electrical Characteristics
B.5 AC Electrical Characteristics
B.6 Embedded Flash Memory Characteristics
B.7 Analogue Characteristics
Appendix C Mechanical Package Drawings
C.1 TQFP128
Appendix D eICE Debug Interface
D.1 Signal Functions
D.2 Handshake
D.3 Abort
D.4 eICE Command and Data Shift
D.5 Clocking and Initial Operation
D.6 eICE_LOADB and Reset
D.7 eICE Registers
D.8 eICE Commands
Appendix E Register Map
Appendix F Interrupt Vectors
Appendix G Port Select Options
G.1 Port A
G.2 Port B
G.3 Port C
G.4 Port D
G.5 Port E
G.6 Port F
G.7 Port G
G.8 Port H
G.9 Port I
G.10 Port J
G.11 Port K
G.12 Port L
Appendix H Port Select Options (Alternate
View)
H.1 Port A
H.2 Port B
H.3 Port C
H.4 Port D
H.5 Port E
H.6 Port F
H.7 Port G
H.8 Port H
H.9 Port I
H.10 Port J
H.11 Port K
H.12 Port L
Appendix I Peripheral Routing Options
I.1 GPIO
I.2 PIO
I.3 DUART
I.4 DUSART
I.5 Timers
I.6 EMI
I.7 EHI
Appendix J External Peripheral Signals
J.1 GPIO
J.2 PIO
J.3 DUART
J.4 DUSART
J.5 Timers
J.6 EMI
J.7 EHI
Appendix K Unused GPIO Signals
Appendix L Contact Information
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