Contents
Previous Chapter
Next Chapter
The Port Configurator is used to select the peripheral signals that appear on the chip level ports of eCOG1X.
Users must select which peripheral signals appear on the pins of the eCOG1X because the eCOG1X contains more peripheral signals than can be fitted into the number of pins on the chip. The eCOG1X contains hardware to allow users to select which peripheral signals appear as external signals. In addition, users have some control over where on the chip the peripheral signals appear.
This feature allows eCOG1X to contain many peripherals and achieve a relatively low pin count for the number of available peripherals, which reduces the system cost.
The configurable pins are grouped into nineteen ports named PortA to PortT (with PortO not included). Each port has either four or eight bits. These pins are named as PortX_n, where X is the port letter and n is the pin number from 0 to 7 (or a number from 0 to 3 for the four bit ports). The selection of peripheral signals is done on a per port rather than per pin basis. The number of configuration options is different for each port.
The operation of the GPIO peripheral ports is slightly different to that of the other peripherals. Each port bit can be configured individually to operate as a GPIO signal, overriding the configuration set by the peripheral port configurator multiplexing. This is discussed in further detail in the GPIO section.
For each port, there is a field in a register that selects the group of peripheral signals that are routed to the port pins. Since each port bit can be set to a GPIO, it is possible to disable a port by setting the respective GPIO port to high impedance. In a similar manner, it is also possible to disable inputs to a peripheral, by using the GPIO feature to disable the input to the peripheral.
The table below summarises the port names, number of pins and number of configuration options.
It is possible to configure the chip so that the same peripheral signal appears on more than one pin. This is allowed. For output signals, all duplicated pins are driven to the same state. For input signals, the pin on the lowest port letter is used as the input and any other pins on higher ports are ignored.
The DUSART supports six serial protocols, of which only two can be in use at the same time. This is explained further in the DUSART section. It is allowed to use a configuration that contains signals from more than two DUSART protocols; the signals belonging to the unused protocol are tristated.
If the full External Memory
Interface or External Host Interface is used, then ports D, E,
F, G, H, I and J are used for the selected interface. The EMI
and EHI cannot both be used simultaneously because they use
the same ports.
Note that not all of these ports are required for all EMI
configurations; for example, if the external memory interface is
configured for an 8 bit data bus and 16 bit address bus, then
port I is available for GPIO. If the address bus is also limited
to 8 bits, then ports F and G are available for other
functions.
The CyanIDE development environment includes a graphical eCOG1 configuration file editor, called the port configurator. This editor incorporates the rules and restrictions for the eCOG1X I/O port and channel assignments. It allows the user to investigate possible chip configurations and pin mappings, and automatically generates the source code for initialising the port configuration registers. The configurator supports multiple eCOG1 devices and packages, including the eCOG1k and eCOG1X variants.
A brief summary of the configuration rules is given below. An understanding of these rules is not necessary in order to use the CyanIDE configuration editor, but may be useful in some cases.
Some application requirements can impose significant restrictions on the eCOG1X configuration options. The following sections highlight some of the main decisions to be made before setting the device configuration.
Note the following recommendations for achieving minimum power consumption when some pins are not used and are left disconnected.
The Port Configurator contains the following registers:
This read-only register can be
read to determine the version of the chip and its
configuration.
For the eCOG1X this returns a value 0x001X.
The register contains the following fields.
This register selects the peripheral signals that are routed to the pins of ports A, B, C and D. Each value in these fields corresponds to a set of peripheral signals.
The register contains the following fields.
This register selects the peripheral signals that are routed to the pins of ports E, F, G and H. Each value in these fields corresponds to a set of peripheral signals.
The register contains the following fields.
This register selects the peripheral signals that are routed to the pins of ports I, J, K and L. Each value in these fields corresponds to a set of peripheral signals.
The register contains the following fields.
This register selects the peripheral signals that are routed to the pins of ports M, N, P and Q. Each value in these fields corresponds to a set of peripheral signals.
The register contains the following fields.
This register selects the peripheral signals that are routed to the pins of ports R, S and T. Each value in these fields corresponds to a set of peripheral signals.
The register contains the following fields.
This read-only register indicates which I/O ports are disabled and not available in the current device or package variant.
The register contains the following fields.
|
hipqrs: Returns a '1' when ports H, I, P, Q, R and S are disabled. |
||
|
fjklm: Returns a '1' when ports F, J, K, L and M are disabled. |
