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Internal clocks and resets for eCOG1X are generated by the System Support Module (SSM).
The operations of the system support module are grouped into two main functional areas. The SSM controls all internal clocks for the eCOG1X CPU and peripherals, and it also controls all CPU and peripheral internal resets. Five clock sources are used to provide all eCOG1X internal system clocks. Two crystal oscillators provide two accurate reference clocks which can be driven into two PLLs providing a further two reference clocks. A relaxation oscillator provides a fifth clock source that requires no external components. eCOG1X provides a controlled power on reset and allows software reset control of the CPU and individual peripherals.
The SSM also provides a module for controlling the CPU clock whilst in sleep mode.
The following diagram shows the principal modules of the SSM.
eCOG1X clock control is provided using four principal functional blocks.
System clocks and PLLs
CPU/memory clock selector
Divider chains
Peripheral clock selectors
Five primary clocks are generated by the system clock generator. These in turn drive the CPU/memory clock select block to control the clocks for the eCOG1X CPU and memories. The peripheral clock divider chains use the primary clocks to provide a series of divided clock outputs. These are selected by the peripheral clock selector block for the various eCOG1X peripherals.
The clock control functional blocks and relationships are shown in the following diagram.
The recommended order for system clock configuration is to set the PLLs as required in the System Clock Generation block, configure the dividers in the CPU/Memory Clock Selector block, configure the peripheral clock divider chains and then to select the clocks to the peripherals as required in the Peripheral Clock Selector. In general, each peripheral can select a divider chain, a divider tap output from the selected divider chain, and a clock prescaler division factor.
This block controls the five primary system clocks.
Two crystal oscillator circuits are available for use with external quartz crystals. The low reference oscillator is used with a low frequency crystal, such as a 32.768kHz watch crystal, and generates the low reference clock. The high reference oscillator is used with a higher frequency crystal, with a frequency between 5MHz and 10MHz, and generates the high reference clock. The recommended high reference crystal frequency is 8.0MHz.
The external quartz crystals used with the two oscillators each require two load capacitors. The maximum load capacitance value for the 32kHz oscillator is 25pF, and for the 8MHz oscillator is 32pF. This includes any package and stray capacitance due to the circuit board layout. The recommended load capacitor values are 10pF for the 32kHz oscillator and 22pF for the 8MHz oscillator. Higher capacitor values increase slightly the power consumption of the oscillator circuits.
A relaxation oscillator provides a third clock source which can be used with no external components for minimum cost systems, provided the application does not require an accurate clock frequency. On devices in the 208BGA package, the relaxation oscillator frequency can be adjusted over a range from 1MHz to 11MHz by changing the value of an external resistor connected from the REXT pin to GND. In the smaller 68QFN and 100QFN packages, the relaxation oscillator runs at the frequency corresponding to an open circuit at the REXT pin with the external resistor not fitted, nominally 1MHz.
Two PLL multipliers are provided to generate a further two higher frequency system clocks. The low frequency PLL is driven by the low reference clock and multiplies the clock frequency by a factor between x2 and x305, providing an output frequency from 65.536kHz to 9.99MHz. The high frequency PLL is normally driven by the high reference clock for best performance with low jitter. It multiplies the selected clock frequency by a factor between x2 and x50, providing an output frequency from 16MHz to 400MHz from the nominal 8.0MHz crystal. The multiplication factors for the two PLLs are set under software control by writing to the low_pll_sel and high_pll_sel fields in the ssm.pll_ctrl register.
The high PLL can also be driven by the low PLL clock or the relaxation oscillator clock. This can save the external components used for the high reference crystal oscillator and the power consumption of the oscillator, but has poorer clock jitter performance. Setting the pll_stepup field in the ssm.pll_cfg register feeds the output of the low PLL into the input of the high PLL. This allows the 32kHz crystal to generate high speed internal clocks up to 400MHz. Setting the relax_pll field in the ssm.pll_cfg register feeds the output of the relaxation oscillator into the input of the high PLL. Note that the user must ensure that the output frequency of the low PLL or the relaxation oscillator remains within the allowed input frequency range for the high PLL (TBD) when either of these two options is enabled.
The oscillators and PLLs are enabled, disabled and their status read from the low_osc, high_osc, relax_osc, low_pll and high_pll fields in the ssm.clk_en1, ssm.clk_dis1 and ssm.sts1 registers. The clock sources are controlled by a hardware interlock to ensure that they cannot be disabled if they are being used to generate the CPU clock and to prevent any condition that might cause the eCOG1X to lockup.
The CPU/memory clock selector contains logic for detecting valid running clocks and selecting the master clock from the available running clocks. It also provides a prescaler and divider to control the frequencies of the clocks to the CPU and memory devices.
Control logic in this block selects the clock source for the master clock in_clk from the available primary clocks. The master clock is used to generate clocks for the memory devices and for the eCOG1X CPU. Two divider blocks are used to generate the memory and cpu clocks mem_clk and cpu_clk. The first divider divides the master clock in_clk by a factor determined by the prescaler field in the ssm.cpu register and generates mem_clk for the on-chip memory blocks. The second divider divides mem_clk by a factor determined by the cpu_clk_div field in the ssm.cpu register and generates cpu_clk for the processor core. The smallest overall division from in_clk to cpu_clk is 2 and the largest is 128.
At power-on, either the high reference clock or low reference clock is selected, dependent on which is available. Software selects the clock source for in_clk by writing to the clk_sel field in the ssm.cfg register. A clock source is only selected successfully if it is enabled and producing an output clock signal. The sts field in the ssm.cpu register indicates which clock source is currently selected.
There are five 16-bit divider chains, each clocked from one of the principal system clock sources, and used to produce the source clock signals for all the peripheral modules. The divider chains provide a range of clock frequencies to the internal peripherals, to be selected according to the speed of the peripheral or any low power requirements of the application. For each peripheral module, one output from one of the five divider chains is selected to provide its clock signal.
Each of the 16 outputs from the five divider chains are fed into the peripheral clock selector block, giving a total of 80 possible clock source frequencies for each peripheral.
Each peripheral can be set to use one of the five divider chains for its clock source. Note that some peripherals are grouped together and share the same divider chain selection.
Three registers are used to select the clock source and divider chain for each peripheral or group. Each peripheral or group has a three-bit field in one of these registers, which selects one of the five clock sources and its associated divider chain.
This register contains bit fields for selecting the clock source and divider chain for the DUART1, DUART2 and DUSART peripherals, and for timer groups 1 and 2.
This register contains bit fields for selecting the clock source and divider chain for the USB and analogue peripherals, the flash memory auto power down timer, and for two groups, (1) ESPI and I2S, and (2) LCD controller and sleep timeout counter.
This register contains a bit field for selecting the clock source and divider chain for the Ethernet MAC and dual smart card (DSCI) peripherals.
An additional register ssm.tmr_src is used to select either timer group 1 or group 2 (and the associated clock source and divider chain) for each of the timer peripherals CNT1, CNT2, PWM1, PWM2, CAP, WDOG, TMR, LTMR and MCPWM.
Six registers, detailed below, are used to select one clock output from the divider chains. The selected divider chain output is used as the clock input to the peripheral. Each peripheral module has a four-bit field in one of these registers, which selects one of the 16 outputs from the divider chain driven by the selected clock source. Setting this field to '1111' selects the fastest output of the divider chain, corresponding to a clock frequency equal to the selected source clock divided by two. Setting the field to '0000' selects the slowest output, corresponding to a clock frequency equal to the selected source clock divided by 216. Other values select the outputs and associated division ratios between these two extremes.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the sleep timeout counter, DUART1, DUART2 and DUSART peripherals.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the CNT1, CNT2, PWM1 and PWM2 peripherals.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the CAP, WDOG, TMR and LTMR peripherals.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the MCPWM, USB, USB wakeup and ESPI peripherals.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the I2S, LCD, ADC1 and ADC2 peripherals.
This register contains bit fields for selecting one of the sixteen divider chain outputs for the DACs, flash auto power down timer, Ethernet MAC and dual smart card (DSCI) peripherals.
Five registers are used to set a clock prescaler division factor for most peripherals. Note that some peripheral modules do not have a clock prescaler at this point in the SSM, and the LCD and MCPWM peripherals have their own separate prescalers within the peripheral block itself. Each peripheral module with a prescaler in the SSM has a four-bit field in one of these registers. The prescaler division factor is equal to one higher than the value of the bit field, thus providing a range of division factors between 1 and 16.
This register contains bit fields to set the clock prescaler division factor for the UART1A, UART1B, UART2A and UART2B peripherals.
This register contains bit fields to set the clock prescaler division factor for the DUSART, CNT1, CNT2 and PWM1 peripherals.
This register contains bit fields to set the clock prescaler division factor for the PWM2, CAP, WDOG and TMR peripherals.
The clock oscillators, PLL multipliers and the associated divider chains are enabled and disabled by setting bit fields in the ssm.clk_en1 and ssm.clk_dis1 registers. Similarly, the peripheral clocks can be individually enabled and disabled.
Setting bit fields in the ssm.clk_en1 and ssm.clk_en2 registers enables the corresponding peripheral clock signals. Setting the relevant fields in the ssm.clk_dis1 and ssm.clk_dis2 registers disables the corresponding peripheral clocks. Bit fields set to '1' in the ssm.sts1 and ssm.sts2 registers indicate that the associated peripheral clocks have been enabled.
The peripheral functions include logic to detect a change of state on any external signal. When a change occurs on a configured peripheral signal, the clock to the peripheral is enabled automatically. This automatic clock activation is disabled by setting the associated bits in the ssm.clk_deact1 and ssm.clk_deact2 registers.
These registers contain bit fields for enabling and disabling the clock signals for the high PLL, low PLL, high reference oscillator, low reference oscillator and relaxation oscillator, and for the Ethernet MAC, USB, LCD, ESPI, I2S, MCPWM, UART1A, UART1B, UART2A, UART2B and DUSART peripherals.
These registers contain bit fields for enabling and disabling the clock signals for the CNT1, CNT2, PWM1, PWM2, CAP, WDOG, TMR, LTMR, ADC1, ADC2, DACs, EMI and DSCI peripherals, and for the flash memory auto power down timer. They also contain a bit field for controlling the relaxation oscillator low power suspend mode.
The two PLL multipliers support a wide range of output frequencies and multiplication factors from a single input reference frequency. When quartz crystals or input clock signals are used with the recommended frequencies, then all possible values for the multiplication factors can be used. If a higher frequency crystal or input clock signal is used, then some multiplication factors should not be used because either the PLL output or the VCO output frequency exceeds the maximum limit.
Note that if the high PLL is used as the memory clock source and the EMI peripheral is used, then the high PLL output frequency must be limited to a maximum of 385MHz. If the EMI peripheral is not used, the maximum high PLL output frequency of 400MHz can be used to generate the internal memory and CPU clocks.
The following table lists the low PLL multiplication factors and shows the VCO and PLL output frequencies for the recommended 32.768kHz crystal. The PLL multiplication factor N is controlled by the value F[8:0] stored in the low_pll_sel bit field of the ssm.pll_ctrl register. The maximum low PLL output frequency is 9.99MHz, and the maximum VCO frequency is 50MHz.
The following table lists the high PLL multiplication factors, and shows the VCO and PLL output frequencies both for the recommended 8.0MHz crystal and for a 10.0MHz crystal. The PLL multiplication factor N is controlled by the value F[6:0] stored in the high_pll_sel bit field of the ssm.pll_ctrl register. The maximum high PLL output frequency is 400MHz, and the maximum VCO frequency is also 400MHz. Note that if a 10MHz crystal is used for the high oscillator, some PLL multiplier selections cannot be used because the VCO frequency exceeds the maximum limit. These are highlighted in red.
The clock sources, PLLs and SSM provide clock signals to the on-chip peripheral modules over a wide frequency range. There are maximum (and in some cases minimum) frequency limits on the clock signals provided by the SSM to the peripheral modules.
The following table lists any limits or constraints on input clock frequencies for the CPU and the on-chip peripherals, after the SSM clock dividers and prescalers. Note that each frequency listed here is the absolute maximum internal clock frequency for the peripheral. This means only that the internal peripheral hardware can be clocked at this maximum frequency, it does not mean that the complete peripheral function including external signals operates successfully at this frequency. Input and output delay times and pin loadings must be taken into account when determining the maximum operating frequency for any peripheral including external signals.
On executing a sleep instruction, the processor enters the sleep state. The CPU is woken from the sleep state on any wakeup event: an interrupt from a peripheral device, an input event on an external pin, or the expiry of the sleep timeout counter.
The SSM supports the CPU operating in the sleep state by controlling the way in which the CPU responds to wakeup events. It is also possible to switch off the CPU and peripheral clocks during the sleep state to save power if required by the application.
Two register bits are used to control the sleep mechanism. These bits are known as the morning and evening bits and are bits 0 and 1 respectively of the sleep control register ssm.sleep. Setting the evening bit clears the morning bit and allows the CPU to go into sleep mode when it executes any subsequent sleep instructions. When the morning bit is set, the CPU executes sleep instructions as nop s (no operation), and the sleep mechanism is disabled.
If an interrupt is generated by a peripheral while the CPU is sleeping, it wakes up and starts to execute the appropriate interrupt service routine. It continues to execute code until the end of the ISR is reached and the rti (return from interrupt) instruction is executed. The CPU then returns to and executes the original sleep instruction. What happens next depends on the state of the morning and evening bits. If the evening bit is set, the CPU returns to sleep mode; however if the morning bit was set by the ISR, then the sleep instruction executes as a nop, resulting in the CPU staying awake, and code execution continues from the next instruction after the sleep.
This mode of operation may be described as 'doze' mode, where the CPU sleeps and is woken by external events. Normal operation is with doze mode enabled. When a wakeup event occurs, the CPU clock and register interface clock are enabled. If the wakeup event also causes an interrupt, then the CPU is awakened from sleep state to execute the interrupt service routine. Setting the doze_dis field in the ssm.wakeup_cfg register inhibits the CPU clock on a wakeup event and hence any further interrupts are not serviced. Conversely, setting the clk_en bit in the ssm.wakeup_cfg register forces the CPU clock and register interface clock to keep running even in the sleep state.
It is recommended that every sleep instruction is immediately followed by code to set the evening bit. This ensures that the CPU is in the evening state when the next sleep instruction is encountered. If the evening bit is not set, then any subsequent sleep instructions are ignored and the CPU does not go into sleep mode.
It should be noted that if an interrupt service routine is running when another interrupt event occurs, then the second interrupt is not serviced until the first service routine has completed and returned.
If an interrupt service routine directly executes a sleep instruction (when the evening bit is set), then the CPU goes into sleep mode, the ISR does not complete and consequently does not return. The interrupt logic does not generate any further interrupts, as the first ISR has not executed the rti instruction and the CPU does not return from interrupt mode to user mode. The CPU stays in the sleep state until the device is reset, or, if enabled, the sleep timeout counter expires causing the CPU to wake up.
It is possible to configure the eCOG1X such that the clocks that drive selected on-chip peripherals are disabled automatically during sleep mode. This allows the user to leave running only the peripherals that are intended to wake the CPU by generating interrupts. The other peripherals then consume only a minimal amount of power during sleep mode as their clock signal is disabled.
Four SSM registers control the behaviour of the peripheral clocks during sleep mode. These are the clock disable on sleep registers ssm.clk_sleep_dis1/2 and the clock enable on wakeup registers ssm.clk_wake_en1/2. These registers are used to select which clocks are disabled automatically when the CPU goes into sleep mode, and which are re-enabled automatically when the CPU wakes up. The contents of the sleep disable and wake enable registers need not be the same; the user may decide to disable a clock on sleep but not enable it automatically on wakeup. The application may later re-enable any clocks left disabled by setting the appropriate bit in the clock enable registers ssm.clk_en1/2. In addition, the clock deactivate registers ssm.clk_deact1/2 may be used to deactivate peripheral clocks and prevent them being restarted on any wakeup event.
The CPU clock and register interface clock signals cpu_clk and if_clk are used to drive the CPU and MMU/peripheral registers respectively. Setting the clk_en bit field to '1' in the ssm.wakeup_cfg register forces these clocks to continue to run whilst the CPU is in sleep mode.
The sleep timeout counter provides a safeguard in case the interrupts that are intended to wake the CPU do not occur. If it is disabled in sleep mode by setting the timeout field in the ssm.clk_sleep_dis2 register, then this safeguard is absent; if the expected interrupts do not occur, the CPU remains in sleep mode until the microcontroller is reset.
Note that the sleep timeout counter has no control field in the ssm.clock_wake_en2 register. This counter is only active in sleep mode.
In combination with the automatic power down of the flash memory, it is possible to configure the eCOG1X to stop the clock from which it is running and so enter a completely static state.
The only clock source that can be used in this way is the relaxation oscillator. When the CPU enters the sleep state and the flash automatically powers down to Stop mode, the relaxation oscillator can then be stopped. When a wakeup event occurs, the relaxation oscillator is restarted and execution resumes.
With the CPU clock source set to the relaxation oscillator, the fd.ssm.clk_dis1.relax_osc bit field must be set. Normally this disables the relaxation oscillator, but since it is selected as the CPU clock source, it remains enabled. The fd.ssm.clk_dis2.relax_osc_suspend bit field must also be set. This configures the relaxation oscillator such that when the CPU is in Sleep state and the flash has automatically changed to the Stop mode, the oscillator is disabled.
Note that when disabling other clock sources and peripheral clocks in this process, the peripheral clock for the flash timer is left enabled. The following example code disables all the clocks appropriately and leaves the flash timer running.
// Disable all the clocks except the flash power down timer // This also enables the relax_osc_suspend mode rg.ssm.clk_dis2 = 0x6FFF; rg.ssm.clk_dis1 = 0xFFFF;
When a sleep instruction is executed and the fd.ssm.sleep.evening bit field is set, the CPU enters the sleep state. Following this, as the CPU has now stopped performing instruction fetch read cycles from the flash memory, the flash timer automatically powers down the flash memory to Stop mode. Once the flash memory is in Stop mode, the relaxation oscillator is disabled automatically and the eCOG1X enters a completely static state. This gives the lowest possible power supply current.
When a wakeup event is received from a GPIO interrupt, the relaxation oscillator is enabled and execution restarts in the same way as waking from normal sleep mode.
This mode is advantageous as it allows a fast start up from sleep mode, but retains the low power consumption associated with using a low frequency clock. If the relaxation oscillator frequency is adjusted to 10MHz with an external tuning resistor, then the wakeup time is approximately 5µs. If the relaxation oscillator frequency is at its default value (approximately 1MHz) with no external tuning resistor, then the wakeup time is approximately 50µs.
A simple test using the eCOG1X processor daughter board from the development kit shows that it requires a standby current of only 5µA on the 1.8V supply in this deep sleep mode.
Important Note:
All internal clocks are stopped in deep sleep mode. Since all eICE
debug interface transfers are clocked by the internal CPU clock
source, this means that in deep sleep mode all eICE commands are
ignored and no debug operations are possible until the device is
woken by an external interrupt event. When debugging a system that
will use deep sleep mode in the final application, it is recommended
that the CyanIDE project is set up for separate
release and debug
build variants, with the debug build modified
such that it does not set the relax_osc_suspend
bit in the ssm.clk_dis2 register. This
leaves the relaxation oscillator running during sleep mode and allows
eICE operations to take place, and uses only slightly more power than
the fully stopped release build.
Wakeup events are generated by a number of sources: an interrupt from an on-chip peripheral, an edge or level detected on a GPIO input, or expiry of the sleep timeout counter.
An external input wakeup event is generated when an event from an external input to the peripheral clock domain interacts with the CPU clock domain. The action of waking up the CPU on an input wakeup event is disabled by setting the wakeon_if_dis field in the ssm.wakeup_cfg register. The default is for input wakeup events to be enabled.
The GPIO signals may be configured to generate interrupts and wake up the processor core on a high or low level, a rising or falling edge or any edge on the selected port pin. GPIO interrupts are controlled by bit fields in three registers, gpio.xy.cfg_edge1, gpio.xy.cfg_edge0 and gpio.xy.int_level. The combination of bit fields in these three registers is used to select the interrupt event. The bit field values are shown in the table below.
GPIO interrupts are enabled by writing a '1' to bit fields in the gpio.xy.int_en registers, and disabled by writing a '1' to bit fields in the gpio.xy.int_dis registers. Interrupt status is read from the gpio.xy.int_sts registers, and interrupts are cleared by writing a '1' to bit fields in the gpio.xy.int_clr registers. See Section 9.9 for further details of the GPIO control registers.
In the event that no interrupts are generated to wake the CPU from the sleep state, a wakeup event may be generated after an interval governed by the sleep timeout counter. This is an 8 bit counter that is clocked from the selected output of one of the five peripheral clock dividers.
The counter is started each time a sleep instruction is executed. A wakeup event occurs when its count reaches zero. When using the 8MHz high reference clock, the maximum timeout period available is of the order of 2.1 seconds, while with the 32.768kHz reference it is 512 seconds. The sleep timeout counter may be disabled by setting the timeout bit in the clock disable on sleep register ssm.clk_sleep_dis2, as described earlier. Note that if no interrupts occur to trigger a wakeup, this may result in the CPU remaining inactive until reset.
Any of the five available clocks may be selected as the clock source for the sleep timeout counter. The selection is made by the timeout_lcd bit field in the ssm.clk_src2 register. Note that the sleep timeout counter and the LCD controller are grouped together and share the same clock source selection. As these are both low speed peripherals, this is not a major restriction.
The corresponding divider chain output tap is selected by setting the 4 bit timeout bit field in the ssm.clk_div1 register. Setting this field to '1111' selects the fastest output of the divider chain, giving a timeout clock frequency equal to the selected source clock divided by two. Setting the field to '0000' selects the slowest output, giving a clock frequency equal to the selected source clock divided by 216. Other values select the outputs and associated division ratios between these two extremes.
The CPU has a recovery period after a wakeup event, during which it does not go back into sleep mode even if it executes another sleep instruction. The CPU must execute code for a minimum of four CPU clock cycles before it is able to go back to sleep. If less than four clocks have elapsed since the wakeup event, the CPU ignores the sleep command and continues to run the subsequent code.
In the majority of cases this does not present a problem as it takes very little code to use up the required minimum number of clock cycles. Care should be taken if two successive sleep instructions are separated by only one or two lines of code in the application.
There is a delay between the time at which the wakeup event occurs and the time at which the CPU starts to execute code. This delay is nominally 16 CPU clock periods.
In the case where an interrupt is generated by an external signal on a GPIO port, the interrupt occurs asynchronously with the CPU clock. This results in up to one extra clock cycle being required, leading to a total of 16 to 17 CPU clock periods of the currently selected CPU clock.
The table below shows the wakeup times for some possible CPU clock configurations.
The SSM provides extended power on reset, CPU reset, and a means to control reset to individual peripheral modules.
When the power supply falls below the power on reset threshold, eCOG1X is held in the reset state. When the power supply rises above the power on reset threshold, the SSM provides an extended version of the external power-on reset input. The reset signal to the eCOG1X is extended and held active while the active clock sources are detected and a master clock is selected. It is then held active for a further 3ms after the external reset signal goes inactive, to prevent the internal reset going inactive before the supply is at the correct operating voltage.
The SSM generates a CPU reset upon the following conditions:
A CPU reset is achieved by writing a '1' to the cpu_rst field in the ssm.rst_set2 register.
During the debug process, the eCOG1X CPU can be reset via the eICE interface by applying the following routine:
The SSM provides control logic to reset one or all of the eCOG1X peripherals whilst leaving the CPU in its running state.
Individual reset of the peripheral devices is performed by setting and then clearing the relevant peripheral set/clr fields in the ssm.rst_set1/2 and ssm.rst_clr1/2 registers. Clearing a reset should be considered as bringing a module into service.
A register interface clock pervades throughout the eCOG1X device. This provides a clock signal to the configuration registers, internal to each peripheral device. This register control clock signal (if_clk) is used in conjunction with a register control reset signal (if_rst). All peripheral devices that have internal configuration registers, and are hence controlled by if_clk and if_rst, can be reset by the if_rst signal. Writing a '1' to the if_rst bit field in the ssm.rst_set2 register resets the peripherals as shown in the Reset Summary section.
Resetting the peripherals must be done with regard to the peripheral clock. The clock to the peripheral should be disabled, the reset asserted then cleared, and then the clock re-enabled. The five clock divider chains should be held in reset while any peripheral clocks they drive are changed.
Note that all peripheral reset signals controlled by the ssm.rst_set1 and ssm.rst_set2 registers are asserted by a power-on reset and remain in the reset state until cleared by software.
The System Support Module contains the following registers:
This register controls the reset signals to the separate peripheral clock domains. It forms a set/clear pair with the ssm.rst_clr1 register. Setting a bit to '1' asserts the internal reset signal for the corresponding clock domain. Reading this register returns zero.
The five divider chains must be held in reset while any clocks they drive are changed.
The register contains the following fields.
This register controls the reset signals to the separate peripheral clock domains. It forms a set/clear pair with the ssm.rst_clr2 register. Setting a bit to '1' asserts the internal reset signal for the corresponding clock domain. Reading this register returns zero.
The five divider chains must be held in reset while any clocks they drive are changed.
The register contains the following fields.
This register controls the reset signals to the separate peripheral clock domains. It forms a set/clear pair with the ssm.rst_set1 register. Setting a bit to '1' clears the internal reset signal for the corresponding clock domain. Reading this register returns the current value of the reset latch bits, with a '1' indicating that the corresponding reset is cleared.
All reset signals are set at power on. It is recommended that the clock to the peripheral module is inactive when the corresponding reset is cleared.
The register contains the following fields.
This register controls the reset signals to the separate peripheral clock domains. It forms a set/clear pair with the ssm.rst_set2 register. Setting a bit to '1' clears the internal reset signal for the corresponding clock domain. Reading this register returns the current value of the reset latch bits, with a '1' indicating that the corresponding reset is cleared.
All reset signals are set at power on. It is recommended that the clock to the peripheral module is inactive when the corresponding reset is cleared.
The register contains the following fields.
This is a real time control register used to enable the clocks in the system. It forms a set/clear pair with the ssm.clk_dis1 register. Writing a '1' to a bit field enables the internal clock signal for the corresponding clock domain. Reading this register returns zero. The clock enable status bits for these clock domains are read via the ssm.sts1 register.
The register contains the following fields.
This is a real time control register used to enable the clocks in the system. It forms a set/clear pair with the ssm.clk_dis2 register. Writing a '1' to a bit field enables the internal clock signal for the corresponding clock domain. Reading this register returns zero. The clock enable status bits for these clock domains are read via the ssm.sts2 register.
The register contains the following fields.
This is a real time control register used to disable the clocks in the system. It forms a set/clear pair with the ssm.clk_en1 register. Writing a '1' to a bit field disables the internal clock signal for the corresponding clock domain. Reading this register returns zero. The clock enable status bits for these clock domains are read via the ssm.sts1 register. When a clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or state change signal.
The register contains the following fields.
This is a real time control register used to disable the clocks in the system. It forms a set/clear pair with the ssm.clk_en2 register. Writing a '1' to a bit field disables the internal clock signal for the corresponding clock domain. Reading this register returns zero. The clock enable status bits for these clock domains are read via the ssm.sts2 register. When a clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or state change signal.
The register contains the following fields.
This is a configuration register used to deactivate selected peripheral clocks. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a clock is deactivated by setting a bit in this register, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a configuration register used to deactivate selected peripheral clocks. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a clock is deactivated by setting a bit in this register, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a real time control register used to disable selected peripheral clocks automatically when the CPU enters sleep mode. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a peripheral clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a real time control register used to disable selected peripheral clocks automatically when the CPU enters sleep mode. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a peripheral clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a real time control register used to enable selected peripheral clocks automatically when the CPU exits from sleep mode. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a peripheral clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a real time control register used to enable selected peripheral clocks automatically when the CPU exits from sleep mode. When a peripheral clock is disabled, it can be enabled automatically by the corresponding clock wakeup signal or by a change of state on one of the peripheral signals. When a peripheral clock is deactivated, it cannot be enabled by its respective hardware generated clock wakeup or peripheral state change signal until the deactivate bit is cleared.
The register contains the following fields.
This is a real time control register used to set the clock source and divider values for the memory interface clock mem_clk, the CPU clock cpu_clk and the register interface clock if_clk.
The register contains the following fields.
This read-only status register provides information about the clock oscillators and PLLs.
The register contains the following fields.
