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The eCOG1X peripherals and I/O can generate interrupt requests in response to events occurring either in the eCOG1X peripherals or off chip. For example, a serial transmit buffer may have been transmitted, an event detected at a GPIO pin, or an ADC conversion completed. Each peripheral has addressable registers which are configured by user software to enable or disable interrupts either on a peripheral or individual interrupt basis. User software also provides an Interrupt Service Routine (ISR) to detect and service the interrupt source.
The eCOG1 CPU has two modes of operation, 'User' and 'Interrupt'. Refer to Section 3 of this document, to the eCOG1 C Compiler Manual, and to the eCOG1 Macro Assembler User Manual for further information and details of required actions by the user ISR.
The eCOG1 CPU core supports up to 64 vectored interrupts from its peripherals. Most of the on-chip peripherals may generate interrupts.
In addition, exceptions may be generated on a watchdog timer underflow, an address error, and on DUSART or DUART errors. Exceptions have higher priority over interrupts, however the mechanism for vector fetch and branch address generation is identical for both exceptions and interrupts. Throughout the rest of this document, the term interrupt is used to denote an exception or an interrupt. The priority of interrupts is as follows:
The following diagram describes the flow of interrupt from source to vector fetch and address generation.
When an enabled interrupt signal is received form one of the peripheral blocks, the priority encoder generates a six bit interrupt vector corresponding to the highest priority active interrupt source. The interrupt vector is passed to the Sync and Validate block, which filters the vector address to determine if a valid interrupt request is being made. The Sync and Validate block then generates an interrupt request and passes the six bit vector to the Address Generation block. The Address Generation block appends 19 '0's to the six bit vector to produce a 25-bit vector address, and a 16-bit value is read from that address in code space. The 16-bit value is sign extended to form a 25-bit code space address, and instruction execution for the interrupt service routine (ISR) starts from this address. It is up to the user's ISR to clear the interrupt status if required so that lower priority interrupts may be detected and serviced.
Note that because the 25-bit code space address for the ISR is constructed by sign-extending the 16-bit value in the vector table, all interrupt service routines must be located within the bottom 64K and top 64K bytes of code space (address ranges 0x0 to 0x00FFFF and 0x1FF0000 to 0x1FFFFFF).
The watchdog timer exception operates
differently from all other interrupts. The first occurrence
of a watchdog timeout generates an exception. The second
occurrence of a watchdog timeout generates a hardware reset
signal on the nRESET_OUT output or the nRESET I/O pin.
Interrupt latency is slightly complicated by the fact that the interrupt signal nearly always has to cross clock domains and be resynchronised. The following example shows the path of a typical interrupt, the PWM1 count transition match:
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Combinational delay through enable and priority encode logic |
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Clocking through to vector fetch mechanism in CPU clock domain |
The combinational delay may be estimated at a few nanoseconds, however this is small compared to the total number of clock cycles and can be neglected. The total latency for this interrupt is therefore 2 PWM1 clock cycles and 6 CPU clock cycles, from assertion at the source to the start of vector fetch. The elapsed time may be calculated from the settings in the SSM for the PWM1 clock and CPU clock frequencies.
In some circumstances this imposes a limit on the rate at which interrupts may be generated repeatedly by a peripheral, because the logic that transfers the interrupt from the peripheral clock domain to the CPU clock domain requires a minimum of three peripheral clock cycles to reset and generate successive interrupts. For these interrupts to be triggered correctly, the shortest interval between interrupts is three peripheral clocks.
The full priority scheme is as follows:
The following table is a full list of interrupt vectors and their addesses in code space for the eCOG1X device. When the specified interrupt is detected, the CPU core fetches the contents of the code space address derived from the interrupt vector. This value is then sign extended from 16 to 25 bits, and execution of the interrupt service routine begins by fetching the instruction at this address.
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Reset vector at location 0x0. User must insert a branch instruction at this address. |
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MMU: access to an unmapped
address
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All of the timer modules can be programmed to generate interrupts depending on their configuration, clock controls and asynchronous inputs. In addition the watchdog timer and capture timers generate exception conditions when an error is detected.
Interrupts are listed below by timer:
Refer to the independent descriptions of each protocol support engine for a description of specific interrupts. Exception interrupts, used to signal error conditions, are grouped together within the USART to provide a single exception for both channels. The following table details what interrupt sources are supplied by the DUSART.
The User Serial Port (USR) specific interrupts are as follows.
The Smart Card Interface (SCI) specific interrupts are as follows.
The Infra Red Interface (IFR) specific interrupts are as follows.
Transmit and receive data queue controls and
interrupts are supplied directly from the associated
USART.
There are no specific interrupts for the UART function of the DUSART; software uses the generic data port flow control interrupts to provide real time feedback of packet exchanges.
There are no specific interrupts for the SPI function of the DUSART; software relies on the generic USART flow control interrupts to provide real time feedback of packet exchanges.
There are no specific interrupts for the I2C function of the DUSART; software relies on the generic USART flow control interrupts to provide real time feedback of packet exchanges.
The DUART specific interrupts are shown in the following table.
The External Host Interface (EHI) module delivers the following interrupts to the CPU.
