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eCOG1X contains an on-chip instruction cache, implemented using fast SRAM. It consists of one bank of 2816 bytes of memory. This fast memory area can be configured as a direct mapped four word 256 line instruction cache, or as additional on-chip RAM.
In addition to increasing the execution speed of the processor, the cache also reduces power consumption when compared with running code from flash. This is because the SRAM used for cache consumes less current than the flash, and the flash is powered down until a cache miss is detected and a new instruction is fetched from flash. In addition, the current consumed by the cache is proportional to the frequency of operation, whereas the flash has a relatively high quiescent current draw whenever it is accessed. Hence if the code for standby (low power) mode is locked into cache, or arranged so that it can all run from cache, very low power standby operation can be achieved.
The MMU has an address translator for mapping the cache bank into data space. This function is required when the cache is used as data RAM. The address translator can set the base address (logical address) in data space where the cache RAM is mapped. There is no physical address setting because the physical base address is always set to 0, and the translator block size is fixed at 4K bytes. Note that the cache RAM does not fill this entire area, and only physical addresses 0x0000 to 0x09FF are available for data storage. Odd addresses between 0x0A00 and 0xBFF can be used to store 8 bit values, and addresses 0xC00 to 0xFFF are unavailable.
In addition to the main instruction cache, a dedicated eight byte prefetch buffer for code space instruction fetch reads is implemented.
The cache holds copies of instructions read from program memory. Each cache location holds a 16 bit instruction, a tag which contains the upper 14 bits of the program address from which the instruction was read, a valid indication bit for each instruction and a lock bit for the entire cache line. The lower bits of the program address come from the address of the instruction within the cache.
During program execution, an instruction fetch first checks the prefetch buffer (if it is enabled), then the main cache. When the main cache is enabled, each access to program memory causes the corresponding location to be fetched from cache and compared against the upper bits from the program address for a tag match (hit). If a hit is detected and the valid bit for that word in the cache line is set, then the instruction from cache is returned and executed. If a miss is detected, wait states are inserted while the correct instruction is fetched from program memory.
Normally, the instruction fetched from program memory is written back into cache. This is called the writeback operation. If the cache has been locked, either as a block or as an individual line, then the instruction is not written back into cache. Instead, the old instruction and tag information are preserved.
The cache is automatically initialised following reset, and becomes available 258 CPU clock cycles later. The prefetch buffer is enabled following reset and is available immediately.
The cache tag memory contains the tag value itself (the high 14 bits of the code space address for the cached instruction words), the valid bits (one for each word in the line), and the lock bit for the entire cache line.
The locking mechanism for the cache can operate in two ways. Either the entire cache can be locked against writeback operations by setting the lk_en bit in the cache.cfg register, or the lk_bit_en bit can be set in the cache.cfg register which allows the individual lines in the cache to be locked against writeback.
Note that if individual lines are locked in the cache, then either the prefetch buffer should be disabled, or it should be ensured that all the words in the line are valid. Otherwise, a cache miss on an invalid word in a locked line causes all four words in that line to be read from program memory into the prefetch buffer from program memory, and the instructions in the prefetch buffer are read in preference to the locked instructions in the cache.
When locking individual lines in the cache, the memory must be mapped as data memory and the line entries manipulated. Once the manipulation of the cache lines is complete, then the memory must be set back to cache mode by setting the main_force_en field in the cache.ctrl register. Do not simply clear the main_dis field in this register; if the lk_bit_en and lk_en bits in the cache.cfg register are both '0', then this automatically initialises the cache before enabling it and the modifications to the cache contents are lost. Clearing the main.dis bit field to '0' has no effect when the lk_bit_en or lk_en bits are set to '1', the cache remains disabled.
When the cache is mapped as data memory, individual lines in the cache are located at a series of locations offset through the memory.
A given program code address is mapped into the cache as follows. Address bit [0] is not used as all instruction fetches are performed as word reads. Address bits [2..1] select the individual instruction word in the cache line, address bits [10..3] select the line within the cache, and address bits [25..11] are stored in the tag value together with the cache line lock bit and the four word valid bits.
Thus an instruction word fetched
from code address 0x123456 is stored as follows:
- at line 0x8A (= code address bits [10..3]),
- in the word 3 area (= code address bits [2..1]),
- with a tag value of 0x0246 (= code address bits [25..11]).
When the cache is mapped as data memory, the cached instruction
word appears at physical address 0x068A, the lower 16 bits of the
tag are stored in 0x088A and the upper 8 bits of the tag in
0x0A8A.
The cache is used by the software development tools to insert breakpoints into code that is stored in read-only memory such as the internal flash rom.
In order to use more than five breakpoints, the cache must be enabled. When the cache is disabled, only the five hardware breakpoints are available for use with code in flash memory.
The cache is designed for maximum performance when used with the internal flash memory and the four word prefetch buffer. It operates correctly on instruction fetch cycles from internal flash, and from external SDRAM with burst mode enabled.
The operation of the write back mechanism on a cache miss, when reading code from any memory other than the internal flash or external SDRAM in burst mode, means that all the other valid bits in the same cache line are cleared, regardless of whether the cache line tag has changed. This renders the cache ineffective when executing code from any memory other than the internal flash or external SDRAM in burst mode. SDRAM burst mode is enabled by setting the burst_en bit in the emi.sdram_cfg register.
The Instruction Cache contains the following registers:
The cache configuration register contains the following fields.
The cache control register contains the following fields.
