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The Memory Management Unit (MMU) allows the combination of a variety of internal and external memories into a single logical memory structure. The memory structure, or memory model, has both code space and data space address locations, because the Harvard architecture CPU has a separate code and data bus. The MMU provides code space translations for program code, and data space translations for variables and constants.
The translation of logical memory addresses to physical memory addresses is required as almost all physical memories start with an address of 0x0000. To avoid any address conflicts due to common memory base addresses and to create a linear address range, a logical memory address to physical memory address translation is provided by the MMU.
All address translations, the translation of logical addresses seen by the CPU to physical addresses presented to physical memories, are provided by translator blocks inside the MMU.
The diagram shows graphically the operation of the MMU. The physical collection of memory devices are arranged logically into a memory model, designed for the required application.
The MMU allows full use of the available addresses and increases the range of memory devices that the processor can access, without needing to increase its address range or to add extra internal memory. A single physical memory can be mapped to both code and data space if required.
The purpose of the MMU is to receive memory access requests from the CPU, select a physical memory depending on the MMU configuration and translate the CPU logical memory address into a physical memory address to the memory device. Address translations are controlled using address translator blocks.
There are 20 translator blocks in the MMU, 7 for code and 13 for data space translations. The following list shows both the code and data space translators and their order of precedence.
The MMU provides a facility to overlap physical memory locations. For instance, in data space, a small piece of flash memory can be located inside the address boundaries of a larger piece of external memory. The result of this is that the two memories have a range of addresses that are common to both. Accesses to this overlapping address range cause an access to the flash memory only, as it has a higher precedence than the external memories (from the above list, flash = 7 and external memories = 10 to 13). Furthermore, owing to the higher priority of the flash, the overlapping address range in the external memory is unavailable for access.
The following diagram shows the available translator blocks and the memories that can be accessed by each block. Note that some physical memory blocks can be mapped into both code and data space, while others can be mapped only into data space. In addition, some physical memories can have more than one area mapped into the same address space, set up with different values for the logical address, physical address and size.
Most translator blocks have three registers to control the translation function: a logical address, a physical address and a size register, as shown below. Some translators have a fixed size, logical or physical address, and therefore do not have the corresponding registers.
The logical address register defines the logical base address that the eCOG1 processor core uses to access a physical memory. The physical address register defines the base address used to access the actual block of memory. The size register controls the size of the block of memory that is mapped by the translator; this is used to detect accesses to areas of the logical address map that do not translate to a physical memory and to raise an MMU address error exception.
Code and data space translators may address the same memory area (map to the same physical address), in which case the programmer must take care not to modify the memory in data space while it is also being used to execute code.
When configuring the logical and physical addresses, note that the value written to the register is the logical or physical byte address shifted right by 9 bits.
A segment size must be an integer power of 2, with a lower limit of 512 bytes (29), and an upper limit of 225 for code space and 217 for data space. For a segment size of 2n, the size register is set to 2n - 1. Both the logical and physical start addresses of the segment must be an integer multiple of the segment size.
The size can be calculated as follows...
size (in bytes) = 512 x (size
register value + 1)
The size register must contain a value of 2n - 1 where n is an integer.
...or taken from the following table, which lists all valid register settings. Other register values are not allowed and give unpredictable results.
After power up, 512 bytes of flash memory and SRAM are mapped into the bottom of code and data space respectively:
The translate enable register (mmu.translate_en) acts as a switch to enable the logical to physical address translation. Each bit of the register contains an enable for each configured memory.
The recommended procedure for configuring the translation blocks is to set the enable bit of the translate register to zero (hence disabling any translation), then to set up the logical, physical and size registers for that memory, and finally to set the relevant memory enable bit to one to enable the translation.
For example, in order to configure an external memory of size 8Mbytes into the code space address range 0x800000 to 0xFFFFFF, the following values are written into the MMU registers.
To increase the size of the flash mapped into code space from 512 bytes (0x00000 to 0x001FF) to 64K bytes (0x00000 to 0x0FFFF), the values in the table below are written to the flash code space block zero translation registers. Note that in this case the logical and physical addresses are unchanged, and the code space enable bit for this first internal flash memory block is reserved as it is always mapped to code space.
The internal SRAM (IRAM) is divided into three banks. Bank 0 is always available, while banks 1 and 2 may be enabled or disabled. The control bits for this are located in the mmu.ram_ctrl register.
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Normally enabled
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The Memory Management Unit contains the following registers:
MMU address translator enable register; setting a bit in this register enables the respective address translator in the MMU. A translator may not be enabled or disabled while data or code is being accessed through it.
The register contains the following fields.
MMU address translator enable register; setting a bit in this register enables the respective address translator in the MMU. A translator may not be enabled or disabled while data or code is being accessed through it.
The register contains the following fields.
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emac_data: When set to '1', this bit enables the Ethernet MAC register block to be mapped into data space. |
This register specifies the top 16 bits of the 25-bit logical start address for the first flash memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_code0_log: Logical start address for the first segment of internal flash memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 10 bits of the 19-bit physical start address for the first flash memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_code0_phy: Physical start address for the first segment of internal flash memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the first flash memory segment to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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flash_code0_size: Size of segment of internal flash memory to be mapped into code space. The allowed segment size range is 512 bytes (29) to 512K bytes (219). |
This register specifies the top 16 bits of the 25-bit logical start address for the internal RAM memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_code_log: Logical start address for a segment of internal memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 6 bits of the 15-bit physical start address for the internal RAM memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_code_phy: Physical start address for a segment of internal memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the internal RAM memory segment to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ram_code_size: Size of segment of internal SRAM to be mapped into code space. The allowed segment size range is 512 bytes (29) to 32K bytes (215). |
This register specifies the top 16 bits of the 25-bit logical start address for the first external memory segment on chip select CS0 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_code0_log: Logical start address for the first external memory segment on CS0 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the first external memory segment on chip select CS0 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_code0_phy: Physical start address for the first external memory segment on CS0 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the first external memory segment on chip select CS0 to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs0_code0_size: Size of the first external memory segment on CS0 to be mapped into code space. The allowed segment size range is 512 bytes (29) to 32M bytes (225). |
This register specifies the top 16 bits of the 25-bit logical start address for the first external memory segment on chip select CS1 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_code0_log: Logical start address for the first external memory segment on CS1 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the first external memory segment on chip select CS1 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_code0_phy: Physical start address for the first external memory segment on CS1 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the first external memory segment on chip select CS1 to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs1_code0_size: Size of the first external memory segment on CS1 to be mapped into code space. The allowed segment size range is 512 bytes (29) to 32M bytes (225). |
This register specifies the top 16 bits of the 25-bit logical start address for the second flash memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_code1_log: Logical start address for the second segment of internal flash memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 10 bits of the 19-bit physical start address for the second flash memory block mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_code1_phy: Physical start address for the second segment of internal flash memory mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the second flash memory segment to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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flash_code1_size: Size of second segment of internal flash memory to be mapped into code space. The allowed segment size range is 512 bytes (29) to 512K words (219). |
This register specifies the top 16 bits of the 25-bit logical start address for the second external memory segment on chip select CS0 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_code1_log: Logical start address for the second external memory segment on CS0 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the second external memory segment on chip select CS0 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_code1_phy: Physical start address for the second external memory segment on CS0 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the second external memory segment on chip select CS0 to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs0_code1_size: Size of the second external memory segment on CS0 to be mapped into code space. The allowed segment size range is 512 bytes (29) to 32M bytes (225). |
This register specifies the top 16 bits of the 25-bit logical start address for the second external memory segment on chip select CS1 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_code1_log: Logical start address for the second external memory segment on CS1 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the second external memory segment on chip select CS1 mapped into code space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_code1_phy: Physical start address for the second external memory segment on CS1 mapped into code space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the second external memory segment on chip select CS1 to be mapped into code space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs1_code1_size: Size of the second external memory segment on CS1 to be mapped into code space. The allowed segment size range is 512 bytes (29) to 32M bytes (225). |
This register specifies the top 8 bits of the 17-bit logical start address for the internal RAM memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_data0_log: Logical start address for a segment of internal memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 6 bits of the 15-bit physical start address for the internal RAM memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_data0_phy: Physical start address for a segment of internal memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the internal RAM (block 0) memory segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ram_data0_size: Size of first segment of internal memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 32K bytes (215). |
This register specifies the top 8 bits of the 17-bit logical start address for the RAM memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_data1_log: Logical start address for a segment of memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 6 bits of the 15-bit physical start address for the RAM memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ram_data1_phy: Physical start address for a segment of RAM memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the internal RAM (block 1) memory segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ram_data1_size: Size of second segment of internal memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 32K bytes (215). |
This register specifies the top 8 bits of the 17-bit logical start address for the first internal flash memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_data0_log: Logical start address for a segment of internal flash memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 10 bits of the 19-bit physical start address for the first internal flash memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_data0_phy: Physical start address for a segment of internal flash memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the first internal flash memory segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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flash_data0_size: Size of segment of internal flash memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the 17-bit logical start address for the second internal flash memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_data1_log: Logical start address for a segment of internal flash memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 10 bits of the 19-bit physical start address for the second internal flash memory block mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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flash_data1_phy: Physical start address for a segment of internal flash memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the second internal flash memory segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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flash_data1_size: Size of segment of internal flash memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the 17-bit logical start address for the cache memory block mapped into data space. The cache memory block has a fixed size of 2048 words and a fixed physical start address of zero. The logical start address must be an integer multiple of the segment size.
The register contains the following field.
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cache_data_log: Logical start address for the cache memory block mapped into data space. This segment is a fixed size of 4096 bytes. |
This register specifies the top 8 bits of the 17-bit logical start address for the external memory (cs0, data block0) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_data0_log: Logical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the external memory (cs0, data block0) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_data0_phy: Physical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the external memory (cs0, data block0) segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs0_data0_size: Size of segment of external memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the 17-bit logical start address for the external memory (cs1, data block0) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_data0_log: Logical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the external memory (cs1, data block0) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_data0_phy: Physical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the external memory (cs1, data block0) segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs1_data0_size: Size of segment of external memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the17-bit logical start address for the external memory (cs0, data block1) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_data1_log: Logical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the external memory (cs0, data block1) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs0_data1_phy: Physical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the external memory (cs0, data block1) segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs0_data1_size: Size of segment of external memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the 17-bit logical start address for the external memory (cs1, data block1) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_data1_log: Logical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 16 bits of the 25-bit physical start address for the external memory (cs1, data block1) segment mapped into data space. Both the logical and physical start addresses must be an integer multiple of the segment size.
The register contains the following field.
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ext_cs1_data1_phy: Physical start address for a segment of external memory mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the size of the external memory (cs1, data block1) segment to be mapped into data space. The size of the segment in bytes is 512 x (register value + 1) and only register values of the form 2n - 1 (where n is an integer) are valid. Setting this register to any other value produces erroneous behaviour.
The register contains the following field.
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ext_cs1_data1_size: Size of segment of external memory to be mapped into data space. The allowed segment size range is 512 bytes (29) to 128K bytes (217). |
This register specifies the top 8 bits of the 17-bit logical start address for the USB peripheral register block mapped into data space. The USB register block has a fixed size of 2048 bytes and a fixed physical start address of zero. The logical start address must be an integer multiple of the segment size.
The register contains the following field.
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ext_usb_data_log: Logical start address for the USB peripheral register block mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
This register specifies the top 8 bits of the 17-bit logical start address for the Ethernet MAC peripheral register block mapped into data space. The Ethernet MAC register block has a fixed size of 512 bytes and a fixed physical start address of zero. The logical start address must be an integer multiple of the segment size.
The register contains the following field.
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ext_emac_data_log: Logical start address for the Ethernet MAC peripheral register block mapped into data space. The value in the register must be shifted up by 9 bits to get the actual start address. |
Flash memory control register. Generally these bits should be considered as configuration bits, but it is necessary to change their state while the processor is running. It is recommended that a slow CPU clock is selected before this register is updated.
The register contains the following fields.
Internal RAM control register. Generally these bits should be considered as configuration bits, but it is necessary to change their state while the processor is running. It is recommended that a slow CPU clock is selected before this register is updated.
The internal RAM is divided into three banks. Bank 0 is always available, while banks 1 and 2 may be enabled or disabled by writing to the bank1_dis and bank2_dis bit fields.
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Normally enabled
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The register contains the following fields.
DMA control register for the USB and Ethernet MAC peripherals. These bits should not be changed while any DMA transfers are in progress.
The register contains the following fields.
Address error interrupt status and clear register.
The register contains the following fields.
This register provides status information for the flash memory mini data cache (data prefetch buffer).
The register contains the following fields.
