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eCOG1X has an advanced high speed, low power CPU with a powerful instruction set targeted at high level languages, in particular C. The CPU is capable of operating at speeds up to 70MHz. Full details of the instruction set are contained in the eCOG1 Macro Assembler User Manual.
The main features of the processor are:
The CPU has a Harvard architecture, which means it has separate buses for code and data spaces. This allows the CPU to fetch instructions and access data at the same time.
The eCOG1 CPU is a 16-bit word orientated machine. The addressable data space is 64Kbytes. The addressable code space is 32Mbytes (16M x 16-bit words). Although the internal memories are small compared to the addressing range, external memories can be added to take advantage of the full addressing range. The internal memories are:
The instruction set supports addressing high and low bytes of the 16-bit data words. The data space can be viewed as either 32K (15-bit address) of 16-bit words, or 64K (16-bit address) of 8-bit bytes.
Bytes are organised in a big-endian manner within 16-bit words or 32-bit long words. The diagram below illustrates this. Big-endian means the most significant part of a data word is stored at the lower address in memory.
The MMU allows the physical memories to be mapped into this logical address space. The MMU and physical memories are described in Section 4, Memory Management Unit.
The CPU contains the following registers:
The eCOG1 C Compiler uses the concept of pseudo-registers for temporary storage of variables. This is used to supplement the limited core register resource to improve code efficiency, at the cost of a small amount of RAM. The compiler uses addresses 0xFFC0 to 0xFFFF as pseudo-registers.
To support fast context switches, the IY register is used as the base address to redirect accesses to data addresses 0xFFC0 to 0xFFFF when using direct addressing in User Mode. When an address in this range is accessed by the program (in direct addressing mode only), the actual address used is the value of the IY register plus the (signed) data address given. This is to support a separate interrupt context and many user mode contexts, and context switching takes place in Interrupt Mode. This means that a context switch does not require storing the pseudo-registers.
In User Mode, direct addressed accesses to 0xFFC0 to 0xFFFF (64 bytes) are redirected to addresses (IY - 64) to (IY - 1) respectively. The redirection does not take place for indirect or indexed addressing modes. In Interrupt Mode, these direct addressed accesses are not redirected and the literal address is used. An additional MMU translator for internal RAM is provided specifically to support this memory region in Interrupt Mode.
The assembler code that executes before the compiled C code starts is responsible for initialising the IY register. This code is provided with the CyanIDE tools as a template in the file "cstartup.asm".
This section is a brief overview of the instruction set; the eCOG1 Macro Assembler User Manual contains a complete description.
Users do not write the PREFIX or MODIFY words;
these are inserted automatically by the assembler.
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Arithmetic/Logic flags as described in Section 3.4.1. |
The bit field values for the Reg and Mode fields in the instruction word are shown in the following tables. These values are used for instructions that support different registers or addressing modes, when there is no specific value given in the above table.
There are three aspects to the state of the processor, all of which are independent.
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Whether the program is
running or stopped.
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This section should be read in conjunction with Section 7.4 and Section 7.6, which discuss the SSM control of sleep and wakeup in more detail.
The processor can be asleep or awake. When the processor is awake, it fetches and executes instructions as normal. When the processor is asleep, no instructions are executed. The sleep instruction puts the processor into the sleep state, provided the evening bit is asserted. If the morning bit is asserted, then the sleep instruction is interpreted as a nop and has no effect.
The processor can be woken up in two ways:
If the processor is woken by the eICE command, then execution starts at the instruction following the sleep instruction that put the processor into sleep state.
If the processor is woken by an interrupt from a peripheral, then execution starts at the associated interrupt handler as defined by the vector table. The interrupt handler can decide whether the interrupt source should cause the processor to continue execution following the interrupt, in which case it must assert the morning bit. When the end of the interrupt service routine is reached and the rti (return from interrupt) instruction is executed, the CPU returns to and executes the original sleep instruction. If the evening bit is set, the CPU returns to the sleep state. If the morning bit is set, then the sleep is interpreted as a nop and execution continues.
The table below gives an analogy for this sequence:
The two processor modes are interrupt mode and user mode. When the processor is in interrupt mode, no interrupts can take place. When the processor is in user mode, an interrupt from an enabled interrupt source takes the processor into interrupt mode.
Software can write to the FLAGS register to change the processor mode, which could be used to implement semaphores by only changing the value of the semaphore when the processor is in interrupt mode. The eCOG1X Macro Assembler User Manual contains details of how to implement this mechanism.
The program that the processor is executing can be running or stopped. The stopped state is normally used only for interactive debugging. When a product is in service, the program is always running.
In order to stop the program, eICE commands must be used to enable break events. This can be done using the CyanIDE debugger. Details of all the eICE commands are listed in Appendix F.8. When break events are enabled, the processor can be stopped in four ways:
execution of a BRK instruction
PC register equals BRK register
When the program is stopped, eICE must be used to start the program running again.
The flags register has eight bits that can be put into three groups.
There are four arithmetic/logic flags:
The Macro Assembler User Manual contains a complete description of which instructions affect these flags and how the flag value is calculated.
There are two interrupt flags:
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This bit is used for indication only and is asserted when a peripheral has caused an interrupt. The software does not need to do anything with this bit. Writes to this bit have no effect. |
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When asserted the processor is in User Mode; when clear the processor is in Interrupt Mode. See Section 3.3.2, Processor Mode for a description of User and Interrupt Mode. This flag bit is cleared by an interrupt event and can be set or cleared by software. |
When an interrupt occurs, the U bit is cleared and no further interrupts can take place. The interrupt handler must reassert this bit and restore the other flags when returning from an interrupt. Asserting the U bit takes the processor from Interrupt Mode to User Mode. In a similar way, users can switch to Interrupt Mode from User Mode at any time by writing '0' to this bit in the flags register. This has the effect of globally disabling interrupts. This is useful for implementing functions that must not be interrupted, such as setting and clearing semaphores.
The mode of the processor determines which set of XH, X and Y registers are accessed by the instructions. When the processor is in Interrupt Mode, instructions access the IXH, IX and IY registers. When the processor is in User Mode, instructions access the UXH, UX and UY registers.
There are some special instructions that
access user mode registers in interrupt mode.
This advanced feature is not normally used. These flags have an effect only when eICE break events are disabled. Break events are described in Appendix F.8, eICE Commands.
These flags are not used by the eICE debugger.
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When asserted, this flag causes a Debug Exception after each instruction. |
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When asserted, this flag causes a Debug Exception when a break event occurs. |
The code in the Debug Exception interrupt handler must test the values of the T and B flags to determine the cause of the interrupt.
Instructions are made up of one or more instruction words. An instruction word is either a basic instruction word, a PREFIX word or a MODIFY word.
All instruction words are 16 bits in size. Basic instructions can be prefixed with MODIFY or PREFIX words. Each of these words adds a 16-bit instruction word to the size of an instruction. The assembler is responsible for generating any MODIFY or PREFIX words, i.e. they do not have to be added to the assembler, they are implied from the instruction mnemonic and operands used.
A basic instruction contains 8 bits of signed operand, which is used to hold the literal value. If an instruction needs a literal value that is larger than 8 bits, then PREFIX word is prefixed to the basic instruction word. Each PREFIX word is 16 bits long and adds a further 8 bits of information to the literal value. The largest literal used by the instruction set is 24 bits, so a maximum of two PREFIX words may be prepended to the basic instruction word to hold literal values.
Some instructions require a MODIFY word to be added to the basic instruction word. The MODIFY word changes the way in which the following instruction word is interpreted.
It is possible for basic instruction words to be prefixed by both a MODIFY word and up to two PREFIX words. In this case the MODIFY word precedes the PREFIX word(s) and the instruction. In the current instruction set none of the instructions that use a MODIFY instruction word need two PREFIX words.
The table below shows all possible instruction formats:
In order to explain the timings of instructions, the execution of an instruction is separated into Fetch and Processing. During the Fetch, the CPU reads code memory and retrieves the instruction word. During Processing, the CPU interprets the instruction word and performs the implied processing. The processing may include the CPU making accesses to data memory.
The CPU has a single instruction prefetch, which means the CPU does Fetches and Processing in parallel. The Fetch for instruction word n+1 takes place at the same time as the Processing for instruction word n. The CPU moves onto the next pair of Fetch/Process when the previous Fetch and the Process have completed.
The diagram below illustrates two possible sequences of instructions. Execution time is measured between the points where the Processing completes.
In the first sequence, the instruction fetch takes longer than the processing for most of the instructions; the result is that the processing of the previous instruction finishes before the next instruction fetch is complete. This is the case for a typical application running from internal flash memory.
The second sequence has shorter instruction fetch times that are completed within the processing time of the previous instruction. This is the case for a typical application running from internal cache.
This shows there is a significant benefit to running from cache rather than flash for the majority of instructions, but not for the slower instructions such as SMULT and UDIV.
The number of clock cycles for a particular instruction varies according to how much of the instruction fetch is overlapped with the processing time of the previous instruction.
In order to calculate the execution time of an instruction, we need to know the number of clock cycles for three stages:
max(0, tFETCH (n) - tPROC (n-1)) + tPROC (n)
The number of clock cycles for an instruction fetch is equal to the number of wait states on the code memory plus one.
The number of clock cycles for instruction processing depends on the type of the instruction:
The table below contains some example instruction timings. The Fetch Wait States column contains (a) 0 or (b) 1; this reflects the usual number of wait states for (a) cache and (b) flash memory when the CPU is running at 50MHz. The figures assume all data space accesses have zero wait states.
For instructions with multiple words, the Cycles to Fetch and Cycles to Process columns contain the number of clocks for each instruction word.
The number of cycles to execute an instruction
is not always constant. When the Fetch time is greater than
one clock cycle, the amount of overlap between Fetch and
Process depends upon the Processing time of the previous
instruction. For the instructions that have a Fetch of one
clock cycle, the duration of the instruction is not
variable. This is because the Fetch is always overlapped
with the previous instruction's processing.
