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2 Overview

eCOG1X is a member of the Cyan Technology eCOG1 family of low cost, low power microcontrollers targeting embedded communications applications. It shares the 16-bit processor core with the eCOG1k devices and offers higher performance, more memory and a number of new peripherals.

Development of application software for eCOG1X is supported by a comprehensive software toolkit called CyanIDE that includes:

2.1 eCOG1X Block Diagram

Figure 1: eCOG1X block diagram

2.2 Feature List

The device pins are connected to 19 I/O ports labelled A to T, of which 8 ports are 4 bits wide and 11 ports are 8 bits wide. Different peripheral functions can be mapped to these ports to define the operation of each pin. The method for configuring the ports is described in Section 8, Port Configurator, and the relationship between ports and pins is described in See Port Select Options.

2.3 eCOG1X Options

The eCOG1X is available in a range of packages and functional options. The following table summarises the different devices available and gives their part numbers.

Table 2: eCOG1X variants

Product no.

Flash

ETH

USB

ADC

DAC

I/Os

Package

eCOG1X0A5

512K

 

 

 

 

44

68QFN

eCOG1X1A5

512K

 

 

4

2

36

68QFN

eCOG1X4A5

512K

 

Y

 

 

40

68QFN

eCOG1X5A5

512K

 

Y

4

2

32

68QFN

eCOG1X8A5

512K

Y

 

 

 

44

68QFN

eCOG1X9A5

512K

Y

 

4

2

36

68QFN

 

eCOG1X10B5

512K

Y

 

11

2

60

100QFN

eCOG1X14B5

512K

Y

Y

11

2

56

100QFN

 

eCOG1X10Z5

512K

Y

 

14

2

120

208BGA

eCOG1X14Z5

512K

Y

Y

14

2

120

208BGA

Package diagrams and pin descriptions for the eCOG1X device variants are given in Appendix A.

2.4 Pin Functions

The following table lists eCOG1X pin names and functions. Note that not all pins are present on all devices, depending on package or functional options.

Table 3: eCOG1X pin functions

Label

Function

I/O

ADC1_Vin1-7

ADC1 analogue inputs

I

ADC2_Vin1-7

ADC2 analogue inputs

I

AGND

Analogue GND

PWR

AVDD

Analogue power supply 1.8V

PWR

DAC1

DAC1 analogue output

O

DAC2

DAC2 analogue output

O

eICE_CLOCK

eICE clock input

I

eICE_LOADB 1

eICE Load Byte handshake signal

I/O

eICE_MISO

eICE Master In Slave Out

O

eICE_MOSI

eICE Master Out Slave In

I

EMAC_TXD0-3

Ethernet MAC Transmit Data

O

EMAC_RXD0-3

Ethernet MAC Received Data

I

EMAC_CLKT

Ethernet MAC Transmit Clock

I

EMAC_CLKR

Ethernet MAC Receive Clock

I

EMAC_RXER

Ethernet MAC Receive Error

I

EMAC_RXDV

Ethernet MAC Received Data Valid

I

EMAC_COL

Ethernet MAC Collision Detect

I

EMAC_CRS

Ethernet MAC Carrier Sense

I

EMAC_TXEN

Ethernet MAC Transmit Enable

O

EMAC_TXER

Ethernet MAC Transmit Error

O

FIL 2

External low PLL filter

 

GND 3

Digital GND

PWR

High_XTAL_In 4

High frequency crystal oscillator input

I

High_XTAL_Out 4

High frequency crystal oscillator output

O

IVDD

Internal core logic power supply 1.8V

PWR

JTCLK

JTAG Test Clock input

I

JTDI

JTAG Test Data Input

I

JTDO

JTAG Test Data Output

O

JTMS

JTAG Test Mode Select

I

Low_XTAL_In 5

Low frequency crystal oscillator input

I

Low_XTAL_Out 5

Low frequency crystal oscillator output

O

NC 6

No Connect

 

nRESET 7

Power-on reset (bidirectional, open-drain)

I/O

nRESET_IN 8

Power-on reset input

I

nRESET_OUT 8

Power-on reset sense output

O

nTEST 9

Test select input

I

PortA_0-7

Port A pins 0-7

I/O

PortB_0-7

Port B pins 0-7

I/O

PortC_0-3

Port C pins 0-3

I/O

PortD_0-3

Port D pins 0-3

I/O

PortE_0-7

Port E pins 0-7

I/O

PortF_0-3

Port F pins 0-3

I/O

PortG_0-3

Port G pins 0-3

I/O

PortH_0-7

Port H pins 0-7

I/O

PortI_0-7

Port I pins 0-7

I/O

PortJ_0-3

Port J pins 0-3

I/O

PortK_0-3

Port K pins 0-3

I/O

PortL_0-3

Port L pins 0-3

I/O

PortM_0-7

Port M pins 0-7

I/O

PortN_07

Port N pins 0-7

I/O

PortP_0-7

Port P pins 0-7

I/O

PortQ_0-7

Port Q pins 0-7

I/O

PortR_0-7

Port R pins 0-7

I/O

PortS_0-7

Port S pins 0-7

I/O

PortT_0-3

Port T pins 0-3

I/O

Rext 10

External resistor to set relaxation oscillator frequency

 

ULPI_CLK 11

USB ULPI Clock input

I

ULPI_DATA0-7

USB ULPI Data bus

I/O

USB_n

USB negative

I/O

USB_p

USB positive

I/O

USBVDD

USB power supply 3.3V

PWR

ULPI_STOP

USB ULPI Stop

O

ULPI_NXT

USB ULPI Next

I

ULPI_DIR

USB ULPI Direction

I

ULPI_RST

USB ULPI Reset

 

VDD

Digital power supply 3.3V

PWR

VPP 12

Flash memory high speed programming power supply

PWR

Vref 13

Analogue reference voltage

 

Notes:

  1. The eICE_LOADB pin should be connected to VDD via a 100 kΩ pull-up resistor for normal operation when the eICE debug port is not in use or disconnected. When the eICE port is used for debugging, a 4.7 kΩ pull-up resistor is recommended to reduce the rise time on this open-drain signal and increase the speed of eICE data transfers. If the system is used with an external eICE programming adaptor, then the external adaptor has the 4.7 kΩ pull-up resistor fitted, and the target system only needs a 100 kΩ pull-up resistor connected to this signal.
    It is also recommended that the eICE input signals (eICE_CLK, eICE_MOSI) are connected to GND via 100 kΩ pull-down resistors as a precaution against noise when the eICE port is not in use or disconnected.
  2. The FIL pin requires external low pass filter components for the low frequency PLL to be fitted. The filter consists of a 2.2 nF capacitor from FIL to GND, in parallel with a 68 nF capacitor and an 8.2 kΩ resistor in series.
  3. The QFN packages have a large central body contact which forms the GND pad.
  4. The external quartz crystal used with the 8 MHz high reference oscillator requires two load capacitors. The maximum load capacitance value for the high reference oscillator is 32 pF, including any package and stray capacitance due to the circuit board layout. The recommended load capacitor value is 22 pF.
    If an external clock source is used instead of the 8 MHz quartz crystal oscillator, then the High_XTAL_Out pin is not connected and the external clock signal is connected to High_XTAL_In.
    If the high reference clock is not required, then High_XTAL_Out is not connected and High_XTAL_In is connected to AGND via a 10 kΩ resistor.
  5. The external quartz crystal used with the 32.768 kHz low reference oscillator requires two load capacitors. The maximum load capacitance value for the low reference oscillator is 25 pF, including any package and stray capacitance due to the circuit board layout. The recommended load capacitor value is 10 pF.
    If an external clock source is used instead of the 32.768 kHz quartz crystal oscillator, then the Low_XTAL_Out pin is not connected and the external clock signal is connected to Low_XTAL_In.
    If the low reference clock is not required, then Low_XTAL_Out is not connected and Low_XTAL_In is connected to AGND via a 10 kΩ resistor.
  6. NC indicates a No Connect, these pins should not be connected in circuit.
  7. On smaller package variants (QFN), the nRESET pin is bidirectional. It is driven low internally as an open-drain output by the on-chip power-on reset supply voltage sense circuit, and is also connected as an input to the device from the pin. This allows the use of an external reset circuit if required.
    The nRESET input has a Schmitt trigger input circuit and an internal pull-up resistor. It is recommended that an external 10 kΩ pull-up resistor is fitted, connecting nRESET to VDD.
  8. On larger package variants (BGA), the nRESET_OUT and nRESET_IN pins are not connected internally. This allows the use of an external reset circuit if required. An active low power-on reset signal must be connected to nRESET_IN for correct operation of the device, either from the internal reset circuit or from an external power-on reset circuit. To use the internal power-on reset circuit, connect nRESET_OUT to nRESET_IN, either directly or via external logic for any additional external reset source such as a pushbutton switch.
    The nRESET_IN input has a Schmitt trigger input circuit and an internal pull-up resistor. The nRESET_OUT output is open-drain with an internal pull-up resistor, and can be used in a wired-OR connection with an external power-on reset if the external device also has an active-low open-drain output. It is recommended that an external 10 kΩ pull-up resistor is fitted, connecting nRESET_IN to VDD.
  9. The nTEST pin is not used in normal applications and should be connected to VDD, either directly or via a 10 kΩ pull-up resistor.
  10. The Rext pin for the external resistor to set the frequency of the relaxation oscillator is available only on the 208BGA package. For all devices in the smaller 68QFN and 100QFN packages, the relaxation oscillator runs at the frequency corresponding to an open circuit at Rext with the external resistor not fitted.
  11. The ULPI_CLK input should be pulled low or tied to GND if the ULPI high-speed USB connection is not used.
  12. The VPP pin is used with a higher voltage supply to support fast programming of the internal flash memory via JTAG. If this function is not required, then the VPP pin should be connected to GND to minimise power consumption in normal operation. If this function is required, then connect VPP to GND via a pull-down resistor or jumper link so that the fast programming supply can be connected.
  13. Applications which use the analogue inputs or outputs with the internal reference voltage must have external decoupling capacitors connected to the Vref pin. The recommended decoupling on this pin is a 100nF ceramic capacitor in parallel with a 4.7µF tantalum or aluminium electrolytic capacitor.

2.5 CPU

The eCOG1X flash based microcontroller contains a 16-bit RISC processor with powerful mathematical instructions. An instruction cache offers improved power consumption over traditional flash based microcontrollers as well as substantial speed benefits. The chip has support for two external 16M-word memories and includes an SDRAM controller.

eCOG1X has a flexible on-chip instruction cache. The cache can be used in multiple configurations or as additional on-chip data RAM if necessary. The instruction cache may be used to increase execution speed and reduce power consumption, by caching instructions fetched from the flash.

A sophisticated clocking scheme allows users to control which parts of the chip are enabled in order to satisfy the demands of low power consumption applications.

2.6 Memory

There are 512Kbytes (256K x 16 bits) of embedded flash memory available on-chip, which can be used for both code and data storage. The flash memory may be programmed one word at a time, and erased in pages of 512 bytes or mass erased all in one go. Blocks of 8Kbytes may be read or write protected.

In addition to the main flash memory block, there are two 4K word (x 16 bits) flash blocks that may be used to store information such as configuration data or serial numbers.

There are 24Kbytes (12K x 16 bits) of internal SRAM which can be used as data or code memory. There is also a 8 byte x 256 line instruction cache which may be disabled and used as an additional 2560 bytes (1280 x 16 bits) of SRAM.

The external memory interface allows connection to a wide range of memory devices including SDRAM, flash, ROM, SRAM and memory mapped peripherals. The chip contains an SDRAM controller that supports a wide range of common SDRAMs and includes automatic refresh hardware.

The internal Memory Management Unit (MMU) maps both internal and external physical memories into the code and data space address maps of the CPU. There are separate address translators for code and data space, meaning that the same physical memory can appear in both sides of the memory map. There are 20 address translators in total for the following memories:

2.7 Interrupts

A hardware interrupt structure provides vectored interrupts for all eCOG1X peripherals, timers and I/O. A set of 64 vectors is available; many of these vectors have more than one source. However, user software can determine from interrupt status registers the precise source of any interrupt.

A hardware interrupt priority scheme handles multiple, simultaneous interrupts. All interrupt sources may be selectively enabled or disabled to provide a high level of configurability for the user application.

2.8 Serial Peripherals

The eCOG1X has a rich set of serial peripherals, including UARTs, I2C, SPI, smart card and infra-red protocol engines. In addition, there is a customisable protocol engine for user defined serial protocols.

The peripherals are implemented as two separate dual UARTs and a hardware dual USART. The DUSART is a multi-protocol peripheral and can be configured to use any two of the protocols listed below:

Each of these peripheral functions has its own clock, reset and interrupt signals, and all can be independently enabled and disabled.

Each UART and USART channel has selectable guard times and timeouts, frame sizes, parity and data rates. They also have power saving features which allow their clocks to be enabled only during reception and transmission. The CPU may also be put to sleep whilst the serial ports are active and woken up on an interrupt.

2.9 Timers

A full set of hardware timer functions is available in eCOG1X, providing eight independent timers capable of performing functions such as clock generation, PWM generation and infra-red signal modulation, in addition to normal timer/counter functions. The user can configure many parameters for each timer, including its clock rate, period or reload value and interrupt enable/disable. Two timers can be configured as counters with an external clock signal. The available timers include:

2.10 Port Configurator

The eCOG1X device contains many more peripherals than can be routed simultaneously to the physical port pins. It contains a flexible port configurator which allows users to choose how the peripheral blocks are connected to the external pins. The result is that the chip has a low pin count for the number of available peripherals and users can select the peripherals they need for their application.

2.11 External Host Interface

The external host interface (EHI) enables fast data transfer between eCOG1X and an external microprocessing device. 16 or 32 bit parallel data can be transferred between eCOG1X and an external host in either Memory Mapped Peripheral (MMP) or Direct Memory Access (DMA) modes.

In MMP mode, the EHI allows random access to the eCOG1X internal SRAM. In DMA mode, rapid data transfer can be achieved using flow control handshaking.

2.12 Analogue Voltage and Temperature Sensors

The internal 12 bit ADCs can be used to measure external voltages in either single ended or differential mode. In addition, two internal sensors allow the ADCs to measure the device temperature and the analogue supply voltage.

2.13 eICE Debugger

The eCOG1X has an embedded In Circuit Emulator (eICE) that allows access to the CPU and the entire register/memory space of the eCOG1X.

The eICE command set has been designed to support interactive debugging of eCOG1 applications. This powerful debugger allows users to develop code and system integrators to debug target systems.

2.14 Recommended Approach for This Document

For users new to the eCOG1X, the following sections describe the essential functions which must be configured to start working with the device:

Users wishing to develop typical embedded applications using eCOG1X should refer to the following sections:

 

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