11 Timer/Counter Module
The TIM timer/counter module
provides a set of timing and counting functions to the eCOG1X
device. Eight independent timers support a range of functions. The
control and configuration structure is made up of a register bank,
asynchronous interfaces between the controlling processor and each
of the counters, and logic that generates interrupts and events to
wake up a sleeping processor.
Available timer functions include a
16 bit timer which may be used as a real-time clock; two general
purpose 16 bit timer/counters, two 16 bit timers with logic to
provide a PWM output function, a 16 bit watchdog timer; a 16 bit
event capture timer, and a 24 bit long interval timer.
The diagram below shows the
interfaces to the TIM module.
Registers in the SSM module control and
configure the separate clocks to the timer functions.
Registers in the Port Configurator configure chip I/O
connections to the timer functions.
11.1 Initialisation
Details of how to configure the
frequencies of the clock sources for the timers are given in
Section 7, System Support Module. Note that
after a power on reset, all timers are disabled and the values
of the load/reload registers are cleared.
Each of the eight available
timers has its own clock and reset input, individually
controlled via the SSM module control interface. Refer to the
descriptions of the clock enable, clock disable, reset set and
reset clear registers for more details. Other SSM registers
include bit fields to select the clock source, divider tap and
prescaler division factor for each timer.
The diagram below shows a more
detailed view of the timers that includes the external
signals.
This table is a summary of the
eight timers, their functions and the external signals.
Table 35: Timer function
summary
|
Function
|
Name
|
Length
|
Direction
|
External Signals
|
I/O
|
|
Timer
|
TMR
|
65536
(16 bits)
|
down
|
|
|
|
Timer/Counter
|
CNT1
|
65536
|
down
|
CNT1_TRIG
|
I
|
|
CNT2
|
65536
|
down
|
CNT2_TRIG
|
I
|
|
Pulse Width
Modulation
|
PWM1
|
65536
|
down
|
PWM1_OUT
|
O
|
|
PWM2
|
65536
|
down
|
PWM2_OUT
|
O
|
|
Capture Timer
|
CAP
|
65536
|
up
|
CAP_TRIG1, CAP_TRIG2,
CAP_TRIG3, CAP_TRIG4, CAP_TRIG5, CAP_TRIG6
|
I
|
|
Watchdog Timer
|
WDOG
|
65536
|
down
|
|
|
|
Long Interval Timer
|
LTMR
|
16777216
(24 bits)
|
down
|
|
|
11.2 Interrupts
All of the timer functions can be
programmed to generate interrupts depending on their current
configuration, clock controls and input. In addition, the
watchdog timer and the capture timers generate exception
conditions when an error is detected (WDOG underflow or CAP
capture timer overflow).
Interrupts are listed below by
timer:
Table 36: Timer interrupts
|
Timer
|
Interrupt
|
Description
|
System Interrupt
|
Vector
|
|
TMR
|
tmr_exp
|
A TMR count strobe has
occurred when the TMR timer value is zero.
|
_int_tmr_exp
|
0x20
|
|
CNT1
|
cnt1_exp
|
A CNT1 count strobe has
occurred when the CNT1 timer/counter value is zero.
|
_int_cnt1_exp
|
0x22
|
|
cnt1_match
|
The CNT1 timer/counter
value is the same as the tim.cnt1_cmp register.
|
_int_nt1_match
|
0x26
|
|
CNT2
|
cnt2_exp
|
A CNT2 count strobe has
occurred when the CNT2 timer/counter value is zero.
|
_int_cnt2_exp
|
0x24
|
|
cnt2_match
|
The CNT2 timer/counter
value is the same as the tim.cnt2_cmp register.
|
_int_nt2_match
|
0x28
|
|
PWM1
|
pwm1_exp
|
A PWM1 count strobe has
occurred when the PWM1 timer value is zero.
|
_int_pwm1_exp
|
0x2A
|
|
pwm1_match
|
The PWM1 timer value is
the same as the tim.pwm1_val
register.
|
_int_pwm1_match
|
0x2E
|
|
PWM2
|
pwm2_exp
|
A PWM2 count strobe has
occurred when the PWM2 timer value is zero.
|
_int_pwm2_exp
|
0x2C
|
|
pwm2_match
|
The PWM2 timer value is
the same as the tim.pwm2_val
register.
|
_int_pwm2_match
|
0x30
|
|
WDOG
|
wdog_exp
|
A WDOG count strobe has
occurred when the watchdog timer value is zero. This is a
special exception case.
|
_ex_wdog_exp
|
0x0A
|
|
LTMR
|
ltmr_exp
|
An LTMR count strobe has
occurred when the LTMR timer value is zero.
|
_int_ltmr_exp
|
0x20
|
|
CAP
|
cap_exp
|
A CAP count strobe has
occurred when the CAP timer is at its maximum value.
|
_int_cap_exp
|
0x32
|
|
cap1
cap2
cap3
cap4
cap5
cap6
|
An event on one of the 6
capture inputs has caused the associated tim.cap_val* register to be loaded with
the current capture count value.
|
_int_cap1
_int_cap2
_int_cap3
_int_cap4
_int_cap5
_int_cap6
|
0x34
0x36
0x38
0x3A
0x3C
0x3E
|
|
cap1_ovwr
cap2_ovwr
cap3_ovwr
cap4_ovwr
cap5_ovwr
cap6_ovwr
|
A second event has
appeared on a capture input before its associated
tim.cap_val* register has
been read. This is an exception.
|
_ex_tim
|
0x10
|
11.3 Reload
All timers can be reloaded
manually. With the exception of the capture timer and the
watchdog timer, the timers can also be set to reload
automatically on the next timer clock after they reach a count
value of zero. For the two timer/counters and the two PWM
timers, this reloads the compare and transition values as well
as the period values. The auto reload function for each timer is
enabled by writing a '1' to the *_auto_re_ld bits in the tim.ctrl_en register. A manual reload can be
forced at any time by writing a '1' to the appropriate bits
in the tim.cmd register.
The timer period values are
programmed via the tim.*_ld
registers. The timer/counter compare match values are programmed
via the tim.cnt*_cmp registers, and
the PWM timer transition values via the tim.pwm*_val registers.
A manual reload of any timer
takes four timer clock periods to complete. This is because the
CPU and timers are all in different asynchronous clock domains,
and data transfers between the timer registers and the CPU
registers require a number of timer clock periods for data
synchronisation.
After a reset, the enable, control and load
value registers are cleared to all '0's. Therefore, all
timers are disabled, auto reload is disabled and load values
are all '0's. Software has to configure and enable any
timer function it needs after a reset.
11.4 Reading the Timer Count
Registers
It is important to understand
that the CPU clock and the timer peripheral clocks are
asynchronous. This means that care is required when reading any
of the three count value registers tmr_cnt, cnt1_cnt or cnt2_cnt while the corresponding timer is
running. Incorrect values may be read from these registers
because the count value may change during the CPU read
cycle.
If it is necessary to read one
of the count value registers while the timer is running, then
the application should read it repeatedly until two successive
reads return the same value. This is a valid technique when the
CPU clock is faster than the timer clock, since there is only a
small probability that the count value changes during the read
cycle.
If the CPU clock is slower than
the timer clock, then the count value always changes during the
read cycle and the value cannot be read successfully without
first stopping the timer.
11.5 Timer
The clock timer TMR is a 16-bit
down count timer. An interrupt is generated when the timer
counts past zero. The count duration may be preset or reset at
any time. When enabled, the timer counts at the tmr_clk timer input clock frequency, which is
controlled via the SSM register block. This timer may be
configured for use as a real time clock.
When a new period value is
written to the timer load register tim.tmr_ld, it is not transferred
immediately to the internal count register. The new period value
is transferred either on the next automatic timer reload when it
passes zero, or on the next manual reload when a '1' is
written to the appropriate timer load bit in the timer command
register tim.cmd. A manual reload
of the timer takes four timer clock periods to complete.
|
Associated registers:
|
|
tim.tmr_ld
|
tim.tmr_cnt
|
11.6 Counter
The two timer/counters CNT1 and
CNT2 are 16-bit down counters. An interrupt is triggered when
the counter passes the value stored in a compare register. A
second interrupt is generated when the counter passes zero. The
count duration may be preset or reset at any time, and reload
can be manual or automatic. In addition these timers may be
configured to count on either or both edges of an external clock
input by writing to the tim.cnt1_cfg.edge bit field.
When enabled as a timer, it
counts at the cnt1_clk (or
cnt2_clk) counter input clock
frequency, which is controlled via the SSM register block.
Alternatively, when enabled as a counter, it counts when a
selected edge occurs on an input clock signal. These
timer/counters are therefore suitable for counting external
events in a target system.
When a new period value or match
value is written to the timer/counter load register or compare
registers (tim.cnt*_ld and
tim.cnt*_cmp), they are not
transferred immediately to the internal counter registers. The
new period value and match value are transferred either on the
next automatic timer/counter reload when it passes zero, or on
the next manual reload when a '1' is written to the
appropriate timer/counter load bit in the timer command register
tim.cmd. A manual reload of the
timer/counter takes four timer clock periods to complete.
In counter mode, the external
clock signal is sampled by the internal counter clock, and when
the selected edge is detected on this input signal, the count
decrement strobe is generated. The internal counter clocks are
derived from the SSM via the peripheral clock divider chains and
the CNT1 or CNT2 prescalers. The counter clock must be set to at
least twice the maximum frequency of the external count input
signal to guarantee that the input signal is sampled correctly
and every change of state is detected.
|
Associated registers:
|
|
tim.cnt1_ld
|
tim.cnt1_cmp
|
tim.cnt1_cfg
|
tim.cnt1_cnt
|
|
tim.cnt2_ld
|
tim.cnt2_cmp
|
tim.cnt2_cfg
|
tim.cnt2_cnt
|
11.7 PWM
The PWM timers are implemented
as 16-bit down counters. An interrupt is generated when the
timer passes a 'transition' value stored in one of the
configuration registers, and a second interrupt is generated
when the timer passes zero. The count duration may be preset or
reset at any time.
When enabled, a timer counts at
the pwm1_clk (or pwm2_clk) pwm timer input clock frequency,
which is controlled via the SSM register block. An output clock
signal inverts on each interrupt (transition or zero value). The
clock transition behaviour is programmable via the pol bit in register tim.pwm*_cfg. The default action is to drive
the clock to logic '1' when the count reaches the transition
value and to logic '0' when the timer reaches zero.
When a new period value or
transition value is written to the PWM timer load register or
compare register (tim.pwm*_ld and
tim.pwm*_val), they are not
transferred immediately to the internal counter registers. The
new period value and match value are transferred on the next
automatic timer/counter reload when it passes zero. This
buffering of the new period and transition values allows them to
be updated at any time in the current timer period, and the new
values are transferred synchronously to the timer with the
automatic reload at the start of the next period. This supports
clean PWM output signal generation with no spurious output
transitions when the new values are written.
New period and transition values
are reloaded manually by writing a '1' to the appropriate
timer load bit in the timer command register tim.cmd. A manual reload of the PWM timer
takes four timer clock periods to complete.
Since the output of this timer
is directly related to a clock signal, it can produce a highly
linear function with respect to time. Typical applications are
to generate a variable frequency output or a pulse width
modulated output. Note that by adding an external RC low-pass
filter, it is possible to use a PWM output to generate a
variable DC level.
The PWM1 timer may be used to
generate a clock signal for the Smart Card Interface function in
the DUSART. When PWM1 is configured for hardware reload, the
automatic reload of the PWM1 count register at the end of the
period is controlled by the smart card clock enable signal.
The PWM2 timer may be used to
generate a carrier frequency for the Infra-Red link function in
the DUSART. When PWM2 is configured for hardware reload, the
automatic reload of the PWM2 count register at the end of the
period is controlled by the infra-red transmit data output
signal.
|
Associated registers:
|
|
tim.pwm1_ld
|
tim.pwm1_val
|
tim.pwm1_cfg
|
|
tim.pwm2_ld
|
tim.pwm2_val
|
tim.pwm2_cfg
|
11.8 Capture Timer
The input capture timer CAP is a
16-bit up counter. An interrupt is generated when the timer
wraps around to zero, and it may be reset to zero at any time.
When enabled, the timer counts at the cap_clk capture timer input clock frequency,
which is controlled via the SSM register block.
It is possible to configure this
timer to monitor for a defined edge event on a port input by
setting up options in register tim.cap_cfg. When the specified edge is
detected, an interrupt is generated and the value of the timer
is copied to a capture register. It is possible to trigger on a
rising, falling or either edge, on up to six chip inputs. The
hardware monitors for the defined edge(s) and copies the capture
timer value into one of six registers. Capture inputs 1-4 store
the all 16 bits of the capture timer value, while capture inputs
5 and 6 store only the high 8 bits of the capture timer value.
The application software has to configure and control the
clearing of the timer. If a subsequent capture edge event occurs
before the software has read the first edge event capture value,
then the hardware overwrites the previous data in the capture
register.
Note that the external capture
input signals are sampled by the internal capture timer clock,
and when the selected edge is detected on any of these input
signals, the capture strobe is generated. The internal capture
timer clock is derived from the SSM via the peripheral clock
divider chains and the capture timer prescaler. It must be set
to at least twice the maximum frequency of the external capture
input signal to guarantee that the input signal is sampled
correctly and every change of state is detected.
|
Associated registers:
|
|
tim.cap_val1
|
tim.cap_val2
|
tim.cap_val3
|
|
tim.cap_val4
|
tim.cap_val5
|
tim.cap_val6
|
|
tim.cap_cfg
|
|
|
11.9 Watchdog Timer
The watchdog timer WDOG is a
16-bit down counter module. The count duration may be preset to
a new value or reset to the current period value at any time.
When enabled, the watchdog timer counts at the wdog_clk watchdog timer input clock frequency,
set up in the SSM register block.
When the watchdog timer counts
down past zero for the first time, a watchdog timeout exception
interrupt is generated and the counter restarts automatically to
begin a new countdown period. If the timer passes zero for a
second time without being reset by the application software,
then a hardware watchdog timeout reset signal is generated on
the power-on reset output pin (nRESET or nRESET_OUT).
|
Associated registers:
|
|
tim.wdog_ld
|
|
11.10 Long Interval Timer
The long interval timer LTMR
consists of a 24-bit down counter, allowing a maximum count of
224. An interrupt is generated
when the timer passes zero. The upper 16 bits of the timer may
be set at any time to the value in a load register; the lower 8
bits are reset to zero when the upper 16 bits are written.
When enabled, the timer counts
at the ltmr_clk long interval
timer input clock frequency, which is controlled via the SSM
register block. By correct configuration of the SSM, it is
possible to set the LTMR input clock to 32kHz divided by
216. This timer can divide this by
a further 224 to produce a very
long interval.
|
Associated registers:
|
|
tim.ltmr_ld
|
|
The LTMR long interval timer has
one limitation. When the timer counts down to zero and the
corresponding auto_re_ld bit is
set, it always reloads the previous period value, ignoring any
new period value written to the tim.ltmr_ld register. It does not
automatically load the new period value. The new period value
can be loaded into the timer when it reaches zero by writing a
'1' to the ltmr_ld bit in the
tim.cmd register. This takes four
timer clock periods to complete.
11.11 Timer/Counter
Registers
The Timer/Counter peripheral
module contains the following registers:
Table 37: Timer/counter
registers
11.11.1 tim.cmd
|
Address: 0xFD7E
|
Reset: 0x0000
|
Type: W
|
Counters may be reloaded or
cleared at any time by writing a '1' to the corresponding
bit in the command register. Reading this register returns
zero.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
7
|
ltmr_ld: Writing a '1' to this bit
sets the upper 16 bits of the long interval timer (LTMR)
register to the value in the tim.ltmr_ld register, and the
remaining lower 8 bits to zero.
|
W
|
|
6
|
wdog_ld: Writing a '1' to this bit
sets the WDOG timer register to the value in the
tim.wdog_ld register.
|
W
|
|
5
|
cap_cnt_clr: Writing a '1' to this
bit resets the capture timer register to the value
zero.
|
W
|
|
4
|
pwm2_ld: Writing a '1' to this bit
sets the PWM2 timer register to the value in the
tim.pwm2_ld register and
the timer compare register to the value in the tim.pwm2_val register.
|
W
|
|
3
|
pwm1_ld: Writing a '1' to this bit
sets the PWM1 timer register to the value in the
tim.pwm1_ld register and
the timer compare register to the value in the tim.pwm1_val register.
|
W
|
|
2
|
cnt2_ld: Writing a '1' to this bit
sets the CNT2 timer/counter register to the value in the
tim.cnt2_ld register and
the internal compare register to the value in the
tim.cnt2_cmp register.
|
W
|
|
1
|
cnt1_ld: Writing a '1' to this bit
sets the CNT1 timer/counter register to the value in the
tim.cnt1_ld register and
the internal compare register to the value in the
tim.cnt2_cmp register.
|
W
|
|
0
|
tmr_ld: Writing a '1' to this bit
sets the clock timer (TMR) register to the value in the
tim.tmr_ld register.
|
W
|
11.11.2 tim.ctrl_en
|
Address: 0xFD80
|
Reset: 0x0000
|
Type: RW
|
This register provides real
time control of various timer functions. Writing a '1' to
the appropriate bit position enables the corresponding
function. Reading from this register returns a '1' in bit
positions for functions that are enabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
15
|
ltmr_cnt: Writing a '1' to this bit
enables the long interval timer.
|
RW
|
|
14
|
wdog_cnt: Writing a '1' to this
bit enables the watchdog timer.
|
RW
|
|
13
|
cap_cnt: Writing a '1' to this
bit enables the capture timer.
|
RW
|
|
12
|
pwm2_cnt: Writing a '1' to this
bit enables the PWM2 timer.
|
RW
|
|
11
|
pwm1_cnt: Writing a '1' to this
bit enables the PWM1 timer.
|
RW
|
|
10
|
cnt2_cnt: Writing a '1' to this
bit enables the CNT2 timer/counter.
|
RW
|
|
9
|
cnt1_cnt: Writing a '1' to this
bit enables the CNT1 timer/counter.
|
RW
|
|
8
|
tmr_cnt: Writing a '1' to this
bit enables the clock timer TMR.
|
RW
|
|
7
|
ltmr_auto_re_ld: Writing a '1'
to this bit enables reload of the LTMR long interval
timer period value on reaching zero. The tim.ltmr_ld register holds the reload
value for the most significant 16 bits of the timer. The
least significant 8 bits are loaded with zero.
|
RW
|
|
4
|
pwm2_auto_re_ld: Writing a '1'
to this bit enables reload of the PWM2 timer period and
transition values on reaching zero.
|
RW
|
|
3
|
pwm1_auto_re_ld: Writing a '1'
to this bit enables reload of the PWM1 timer period and
transition values on reaching zero.
|
RW
|
|
2
|
cnt2_auto_re_ld: Writing a '1'
to this bit enables reload of the CNT2 timer/counter
period and compare values on reaching zero.
|
RW
|
|
1
|
cnt1_auto_re_ld: Writing a '1'
to this bit enables reload of the CNT1 timer/counter
period and compare values on reaching zero.
|
RW
|
|
0
|
tmr_auto_re_ld: Writing a '1' to
this bit enables reload of the TMR timer period value on
reaching zero.
|
RW
|
11.11.3 tim.ctrl_dis
|
Address: 0xFD82
|
Reset: 0x0000
|
Type: W
|
This register provides real
time control of the various timer functions. Writing a '1'
to the appropriate bit position disables the corresponding
function. Reading from this register returns zero.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
15
|
ltmr_cnt: Writing a 1' to this bit
disables the long interval timer.
|
W
|
|
14
|
wdog_cnt: Writing a '1' to this
bit disables the watchdog timer.
|
W
|
|
13
|
cap_cnt: Writing a '1' to this
bit disables the capture timer.
|
W
|
|
12
|
pwm2_cnt: Writing a '1' to this
bit disables the PWM2 timer.
|
W
|
|
11
|
pwm1_cnt: Writing a '1' to this
bit disables the PWM1 timer.
|
W
|
|
10
|
cnt2_cnt: Writing a '1' to this
bit disables the CNT2 timer/counter.
|
W
|
|
9
|
cnt1_cnt: Writing a '1' to this
bit disables the CNT1 timer/counter.
|
W
|
|
8
|
tmr_cnt: Writing a '1' to this
bit disables the clock timer TMR.
|
W
|
|
7
|
ltmr_auto_re_ld: Writing a '1'
to this bit disables reload of the LTMR long interval
timer period value on reaching zero.
|
W
|
|
4
|
pwm2_auto_re_ld: Writing a '1'
to this bit disables reload of the PWM2 timer period and
transition values on reaching zero.
|
W
|
|
3
|
pwm1_auto_re_ld: Writing a '1'
to this bit disables reload of the PWM1 timer period and
transition values on reaching zero.
|
W
|
|
2
|
cnt2_auto_re_ld: Writing a '1'
to this bit disables reload of the CNT2 timer/counter
period and compare values on reaching zero.
|
W
|
|
1
|
cnt1_auto_re_ld: Writing a '1'
to this bit disables reload of the CNT1 timer/counter
period and compare values on reaching zero.
|
W
|
|
0
|
tmr_auto_re_ld: Writing a '1' to
this bit disables reload of the TMR timer period value
on reaching zero.
|
W
|
11.11.4 tim.tmr_ld
|
Address: 0xFD84
|
Reset: 0x0000
|
Type: RW
|
The load value for the clock
timer TMR.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
tmr_ld: The load value for the clock
timer TMR.
The period for the timer is given by the input clock period
times this value plus one. When the timer is enabled, it
counts down from its current value to zero.
A new value written to
this register is transferred to the internal timer
register only on the next timer reload. If auto reload
is enabled by the tmr_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the load value in the tim.tmr_ld register. Writing a
'1' to the tmr_ld bit
in the tim.cmd register
immediately loads the timer register with the load
value.
An interrupt when the
timer passes zero is enabled by writing a '1' to the
tmr_exp bit in the
tim.int_en1 register and is
disabled by writing a '1' to the tmr_exp bit in the tim.int_dis1 register.
|
RW
|
11.11.5 tim.cnt1_ld
|
Address: 0xFD86
|
Reset: 0x0000
|
Type: RW
|
The load value for
timer/counter CNT1.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt1_ld: The load value for
timer/counter CNT1.
The period for the timer/counter is given by the input
clock period times this value plus one. When the
timer/counter is enabled, it counts down from its current
value to zero.
A new value written to
this register is transferred to the internal counter
register only on the next counter reload. If auto reload
is enabled by the cnt1_auto_re_ld bit in the tim.ctrl_en register, then when the
counter value reaches zero, the next clock edge reloads
the counter with the load value in this register. It
also reloads the counter compare register with the
compare value in the tim.cnt1_cmp register. Writing a
'1' to the cnt1_ld bit
in the tim.cmd register
immediately loads the counter registers with the load
value and compare value.
An interrupt when the
timer/counter passes zero is enabled by writing a
'1' to the cnt1_exp bit
in the tim.int_en1 register
and is disabled by writing a '1' to the cnt1_exp bit in the tim.int_dis1 register.
|
RW
|
11.11.6 tim.cnt1_cmp
|
Address: 0xFD88
|
Reset: 0x0000
|
Type: RW
|
The compare value for
CNT1.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt1_cmp: The compare value for
timer/counter CNT1.
When the timer/counter is enabled and reaches this compare
value, the next clock edge triggers a counter match
event.
A new value written to
this register is transferred to the counter internal
compare register only on the next counter reload. If
auto reload is enabled by the cnt1_auto_re_ld bit in the tim.ctrl_en register, then when the
counter value reaches zero, the next clock edge reloads
the counter with the load value in the tim.cnt1_ld register, and reloads the
compare register with the compare value in the tim.cnt1_cmp register. Writing a
'1' to the cnt1_ld bit
in the tim.cmd register
immediately loads the counter registers with the load
value and compare value.
An interrupt on the
timer/counter match event is enabled by writing a
'1' to the cnt1_match
bit in the tim.int_en1
register and is disabled by writing a '1' to the
cnt1_match bit in the
tim.int_dis1 register.
|
RW
|
11.11.7 tim.cnt1_cfg
|
Address: 0xFD8A
|
Reset: 0x0000
|
Type: RW
|
Configuration value for
timer/counter CNT1. This register should only be modified when
the associated counter is disabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
2
|
ext: If set to '0', the timer
counts at the internal timer clock rate.
If set to '1', the counter counts clock events on
an asynchronous external input. In this case, the active
clock signal edges are defined by the edge bit field below.
In counter mode, the
external clock signal is sampled by the internal counter
clock for CNT1, and when the selected edge is detected
on this input signal, the count decrement strobe is
generated. The internal counter clock is derived from
the SSM via the peripheral clock divider chain and the
CNT1 prescaler. The counter clock must be set to at
least twice the maximum frequency of the external count
input signal to guarantee that the input signal is
sampled correctly and every change of state is
detected.
|
RW
|
|
1:0
|
edge: The counter may be set to clock on
a rising or falling edge of the external clock input, or
on both edges. This field can have the following
values.
'00': both:
Count on both rising and falling edges of the input.
'01': rising:
Count on rising edges of the input.
'10': falling:
Count on falling edges of the input.
|
RW
|
11.11.8 tim.cnt2_ld
|
Address: 0xFD8C
|
Reset: 0x0000
|
Type: RW
|
The load value for CNT2.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt2_ld: The load value for
timer/counter CNT2.
The period for the timer/counter is given by the input
clock period times this value plus one. When the
timer/counter is enabled, it counts down from its current
value to zero.
A new value written to
this register is transferred to the internal counter
register only on the next counter reload. If auto reload
is enabled by the cnt2_auto_re_ld bit in the tim.ctrl_en register, then when the
counter value reaches zero, the next clock edge reloads
the counter with the load value in this register. It
also reloads the counter compare register with the
compare value in the tim.cnt2_cmp register. Writing a
'1' to the cnt2_ld bit
in the tim.cmd register
immediately loads the counter registers with the load
value and compare value.
An interrupt when the
timer/counter passes zero is enabled by writing a
'1' to the cnt2_exp bit
in the tim.int_en1 register
and is disabled by writing a '1' to the cnt2_exp bit in the tim.int_dis1 register.
|
RW
|
11.11.9 tim.cnt2_cmp
|
Address: 0xFD8E
|
Reset: 0x0000
|
Type: RW
|
The compare value for
CNT2.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt2_cmp: The compare value for
timer/counter CNT2.
When the timer/counter is enabled and reaches this compare
value, the next clock edge triggers a counter match
event.
A new value written to
this register is transferred to the counter internal
compare register only on the next counter reload. If
auto reload is enabled by the cnt2_auto_re_ld bit in the tim.ctrl_en register, then when the
counter value reaches zero, the next clock edge reloads
the counter with the load value in the tim.cnt2_ld register, and reloads the
compare register with the compare value in the tim.cnt2_cmp register. Writing a
'1' to the cnt2_ld bit
in the tim.cmd register
immediately loads the counter registers with the load
value and compare value.
An interrupt on the
timer/counter match event is enabled by writing a
'1' to the cnt2_match
bit in the tim.int_en1
register and is disabled by writing a '1' to the
cnt2_match bit in the
tim.int_dis1 register.
|
RW
|
11.11.10 tim.cnt2_cfg
|
Address: 0xFD90
|
Reset: 0x0000
|
Type: RW
|
Configuration value for
timer/counter CNT2. This register should only be modified when
the associated counter is disabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
2
|
ext: If set to '0', the timer
counts at the internal timer clock rate.
If set to '1', the counter counts clock events on
an asynchronous external input. In this case, the active
clock signal edges are defined by the edge bit field below.
In counter mode, the
external clock signal is sampled by the internal counter
clock for CNT2, and when the selected edge is detected
on this input signal, the count decrement strobe is
generated. The internal counter clock is derived from
the SSM via the peripheral clock divider chain and the
CNT2 prescaler. The counter clock must be set to at
least twice the maximum frequency of the external count
input signal to guarantee that the input signal is
sampled correctly and every change of state is
detected.
|
RW
|
|
1:0
|
edge: The counter may be set to clock on
a rising or falling edge of the external clock input, or
on both edges. This field can have the following
values.
'00': both:
Count on both rising and falling edges of the input.
'01': rising:
Count on rising edges of the input.
'10': falling:
Count on falling edges of the input.
|
RW
|
11.11.11 tim.pwm1_ld
|
Address: 0xFD92
|
Reset: 0x0000
|
Type: RW
|
The load value for timer
PWM1.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
pwm1_ld: The load value for timer PWM1.
The period for the timer is given by the input clock period
times this value plus one. When the timer is enabled, it
counts down from its current value to zero.
A new value written to
this register is transferred to the internal timer
register only on the next timer reload. If auto reload
is enabled by the pwm1_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the load value in this register and the
timer compare register with the transition value in the
tim.pwm1_val register.
Writing a '1' to the pwm1_ld bit in the tim.cmd register immediately loads
the timer registers with the load value and transition
value.
An interrupt when the
timer passes zero is enabled by writing a '1' to the
pwm1_exp bit in the
tim.int_en1 register and is
disabled by writing a '1' to the pwm1_exp bit in the tim.int_dis1 register.
|
RW
|
11.11.12 tim.pwm1_val
|
Address: 0xFD94
|
Reset: 0x0000
|
Type: RW
|
The transition value for timer
PWM1.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
pwm1_val: The transition value for timer
PWM1.
When the timer is enabled and counts down to this
transition value, the associated output signal changes
state on the next clock edge.
A new value written to
this register is transferred to the timer internal
compare register only on the next timer reload. If auto
reload is enabled by the pwm1_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the load value in the tim.pwm1_ld register and the compare
register with the transition value in the tim.pwm1_val register. Writing a
'1' to the pwm1_ld bit
in the tim.cmd register
immediately loads the timer registers with the load and
transition values.
An interrupt on the
timer match event is enabled by writing a '1' to the
pwm1_match bit in the
tim.int_en1 register and is
disabled by writing a '1' to the pwm1_match bit in the tim.int_dis1 register.
|
RW
|
11.11.13 tim.pwm1_cfg
|
Address: 0xFD96
|
Reset: 0x0000
|
Type: RW
|
Configuration value for timer
PWM1. This register should only be modified when the
associated timer is disabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
2
|
pol: This bit sets the initial value of
the output signal following a load command or a timer
reload. The output signal is inverted when the timer
reaches the transition value.
|
RW
|
|
1
|
hw_reload_polarity: If hardware
controlled automatic reload is selected (auto_re_ld
enabled, sw_reload disabled), then this bit selects the
sense of the hardware reload control. If set to
'1', then automatic reload is enabled when the
hardware control signal is '0'.
For timer PWM1, the hardware reload signal is derived from
the smart card clock enable signal.
|
RW
|
|
0
|
sw_reload: Writing a '1' to this
bit configures the PWM1 timer for software controlled
automatic reload. If the pwm1_auto_re_ld bit is set to
'1' in the tim.ctrl_en register, then the timer
is automatically reloaded with the values in registers
tim.pwm1_ld and tim.pwm1_val when the timer passes
zero.
Writing a '0' to this bit selects hardware
controlled automatic reload. For timer PWM1, the smart card
clock enable signal enables or disables the automatic
reload of the PWM1 registers that occurs when the timer
passes zero.
|
RW
|
11.11.14 tim.pwm2_ld
|
Address: 0xFD98
|
Reset: 0x0000
|
Type: RW
|
The load value for PWM2.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
pwm2_ld: The load value for timer PWM2.
The period for the timer is given by the input clock period
times this value plus one. When the timer is enabled, it
counts down from its current value to zero.
A new value written to
this register is transferred to the internal timer
register only on the next timer reload. If auto reload
is enabled by the pwm2_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the load value in this register and the
timer compare register with the transition value in the
tim.pwm2_val register.
Writing a '1' to the pwm2_ld bit in the tim.cmd register immediately loads
the timer registers with the load value and transition
value.
An interrupt when the
timer passes zero is enabled by writing a '1' to the
pwm2_exp bit in the
tim.int_en1 register and is
disabled by writing a '1' to the pwm2_exp bit in the tim.int_dis1 register.
|
RW
|
11.11.15 tim.pwm2_val
|
Address: 0xFD9A
|
Reset: 0x0000
|
Type: RW
|
The transition value for timer
PWM2.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
pwm2_val: The transition value for timer
PWM2.
When the timer is enabled and counts down to this
transition value, the associated output signal changes
state on the next clock edge.
A new value written to
this register is transferred to the timer internal
compare register only on the next timer reload. If auto
reload is enabled by the pwm2_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the load value in the tim.pwm2_ld register and the compare
register with the transition value in the tim.pwm2_val register. Writing a
'1' to the pwm2_ld bit
in the tim.cmd register
immediately loads the timer registers with the load and
transition values.
An interrupt on the
timer match event is enabled by writing a '1' to the
pwm2_match bit in the
tim.int_en1 register and is
disabled by writing a '1' to the pwm2_match bit in the tim.int_dis1 register.
|
RW
|
11.11.16 tim.pwm2_cfg
|
Address: 0xFD9C
|
Reset: 0x0000
|
Type: RW
|
Configuration value for timer
PWM2. This register should only be modified when the
associated timer is disabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
2
|
pol: This bit sets the initial value of
the output signal, following a load command or a
reload/wrap. The output signal is inverted when the
timer reaches the transition value.
|
RW
|
|
1
|
hw_reload_polarity: If hardware
controlled automatic reload is selected (auto_re_ld
enabled, sw_reload disabled), then this bit selects the
sense of the hardware reload control. If set to
'1', then automatic reload is enabled when the
hardware control signal is '0'.
For timer PWM2, the hardware reload signal is derived from
the IFR Tx data output signal.
|
RW
|
|
0
|
sw_reload: Writing a '1' to this
bit configures the PWM2 timer for software controlled
automatic reload. If the pwm2_auto_re_ld bit is set to
'1' in the tim.ctrl_en register, then the timer
is automatically reloaded with the value in registers
tim.pwm2_ld and tim.pwm2_val when the timer passes
zero.
Writing a '0' to this bit selects hardware
controlled automatic reload. For timer PWM2, the IFR Tx
data output signal enables or disables the automatic reload
of the PWM2 registers that occurs when the timer passes
zero.
|
RW
|
11.11.17 tim.cap_cfg
|
Address: 0xFD9E
|
Reset: 0x0000
|
Type: RW
|
Configuration values for the
input capture timer. This register should only be modified
when the capture timer is disabled.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
11:10
|
edge_cap6: Defines the trigger edge for
capture events on input 6. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
|
9:8
|
edge_cap5: Defines the trigger edge for
a capture events on input 5. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
|
7:6
|
edge_cap4: Defines the trigger edge for
a capture events on input 4. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
|
5:4
|
edge_cap3: Defines the trigger edge for
a capture events on input 3. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
|
3:2
|
edge_cap2: Defines the trigger edge for
a capture events on input 2. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
|
1:0
|
edge_cap1: Defines the trigger edge for
a capture events on input 1. This field can have one of
the following values.
'01': rising:
Capture on rising edge.
'10': falling:
Capture on falling edge.
'11': both:
Capture on both edges.
|
RW
|
11.11.18 tim.wdog_ld
|
Address: 0xFDA0
|
Reset: 0x0000
|
Type: RW
|
The load value for the
watchdog timer WDOG.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
wdog_ld: The load value for the watchdog
timer WDOG.
The watchdog timer period is given by the input clock
period times the load value plus one.
When the watchdog timer
is enabled, it counts down from its current value to
zero. If the timer value reaches zero, the next clock
edge reloads the timer with the load value and triggers
a watchdog interrupt. If the watchdog counts down to
zero a second time without being reset, then it
generates a hardware reset output signal.
Writing a '1' to the
wdog_ld bit in the
tim.cmd register
immediately loads the timer with the load value in this
register.
|
RW
|
11.11.19 tim.ltmr_ld
|
Address: 0xFDA2
|
Reset: 0x0000
|
Type: RW
|
The load value for the upper
16 bits of the long interval timer LTMR.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
ltmr_ld: The load value for the long
interval timer LTMR.
The period for the timer is given by the input clock period
times this value plus one, times 256.
When the LTMR is
enabled, it counts down from its current value to zero.
If auto reload is enabled by the ltmr_auto_re_ld bit in the tim.ctrl_en register, then when the
timer value reaches zero, the next clock edge reloads
the timer with the previous load value.
Writing a '1' to the
ltmr_ld bit in the
tim.cmd register
immediately loads the upper 16 bits of the timer with
the new load value in this register, and the lower 8
bits are reset to zero.
|
RW
|
11.11.20 tim.tmr_cnt
|
Address: 0xFDA4
|
Reset: 0xFFFF
|
Type: R
|
The TMR timer register value.
Note that reading this register while the timer is running may
return unstable values because the timer clock and CPU clock
are asynchronous. If it is necessary to read this register
while the timer is running, then the application should read
it repeatedly until two successive reads return the same
value.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
tmr_cnt: The current value of the TMR
timer register.
|
R
|
11.11.21 tim.cnt1_cnt
|
Address: 0xFDA6
|
Reset: 0xFFFF
|
Type: R
|
The CNT1 timer/counter
register value. Note that reading this register while the
timer is running may return unstable values because the timer
clock and CPU clock are asynchronous. If it is necessary to
read this register while the timer is running, then the
application should read it repeatedly until two successive
reads return the same value.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt1_cnt: The current value of the CNT1
timer/counter register.
|
R
|
11.11.22 tim.cnt2_cnt
|
Address: 0xFDA8
|
Reset: 0xFFFF
|
Type: R
|
The CNT2 timer/counter
register value. Note that reading this register while the
timer is running may return unstable values because the timer
clock and CPU clock are asynchronous. If it is necessary to
read this register while the timer is running, then the
application should read it repeatedly until two successive
reads return the same value.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cnt2_cnt: The current value of the CNT2
timer/counter register.
|
R
|
11.11.23 tim.cap_val1
|
Address: 0xFDAA
|
Reset: 0x0000
|
Type: R
|
The capture timer value for
capture input 1. Reading this register automatically clears
the cap1 interrupt status bit in
the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cap_val1: The 16 bit capture timer value
for capture input 1.
This register is cleared automatically when it is read.
|
R
|
11.11.24 tim.cap_val2
|
Address: 0xFDAC
|
Reset: 0x0000
|
Type: R
|
The capture timer value for
capture input 2. Reading this register automatically clears
the cap2 interrupt status bit in
the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cap_val2: The 16 bit capture timer value
for capture input 2.
This register is cleared automatically when it is read.
|
R
|
11.11.25 tim.cap_val3
|
Address: 0xFDAE
|
Reset: 0x0000
|
Type: R
|
The capture timer value for
capture input 3. Reading this register automatically clears
the cap3 interrupt status bit in
the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cap_val3: The 16 bit capture timer value
for capture input 3.
This register is cleared automatically when it is read.
|
R
|
11.11.26 tim.cap_val4
|
Address: 0xFDB0
|
Reset: 0x0000
|
Type: R
|
The capture timer value for
capture input 4. Reading this register automatically clears
the cap4 interrupt status bit in
the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
15:0
|
cap_val4: The 16 bit capture timer value
for capture input 4.
This register is cleared automatically when it is read.
|
R
|
11.11.27 tim.cap_val5
|
Address: 0xFDB2
|
Reset: 0x0000
|
Type: R
|
The capture timer value (high
8 bits only) for capture input 5. Reading this register
automatically clears the cap5
interrupt status bit in the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
7:0
|
cap_val5: The 8 bit capture timer value
for capture input 5.
This register is cleared automatically when it is read.
|
R
|
11.11.28 tim.cap_val6
|
Address: 0xFDB4
|
Reset: 0x0000
|
Type: R
|
The capture timer value (high
8 bits only) for capture input 6. Reading this register
automatically clears the cap6
interrupt status bit in the tim.int_sts2 register.
The register contains the
following field.
|
Bits
|
Field
|
Type
|
|
7:0
|
cap_val6: The 8 bit capture timer value
for capture input 6.
This register is cleared automatically when it is read.
|
R
|
11.11.29 tim.int_sts1
|
Address: 0xFDB6
|
Reset: 0x0000
|
Type: R
|
Timer interrupt status. Shows
the current status of each timer, and may also be used to
detect the source of an interrupt.
|
Bits
|
Field
|
Type
|
|
11
|
ltmr_exp: This bit is set on the next
long interval timer clock when the long interval timer
value is zero.
|
R
|
|
10
|
wdog_exp: This bit is set on the next
watchdog timer clock when the watchdog timer value is
zero.
|
R
|
|
9
|
pwm2_match: This bit is set on the next
PWM2 timer clock when the PWM2 timer value is equal to
the transition value in the tim.pwm2_val register.
|
R
|
|
8
|
pwm2_exp: This bit is set on the next
PWM2 timer clock when the PWM2 timer value is zero. It
is set regardless of the value of the PWM2 timer auto
reload control.
|
R
|
|
7
|
pwm1_match: This bit is set on the next
PWM1 timer clock when the PWM1 timer value is equal to
the transition value in the tim.pwm1_val register.
|
R
|
|
6
|
pwm1_exp: This bit is set on the next
PWM1 timer clock when the PWM1 timer value is zero. It
is set regardless of the value of the PWM1 timer auto
reload control.
|
R
|
|
5
|
cnt2_match: This bit is set on the next
CNT2 timer/counter clock when the CNT2 timer/counter
value is equal to the compare value in the cnt2_cmp_val register.
|
R
|
|
4
|
cnt2_exp: This bit is set on the next
CNT2 timer/counter clock when the CNT2 timer/counter
value is zero. It is set regardless of the value of the
CNT2 auto reload control.
|
R
|
|
3
|
cnt1_match: This bit is set on the next
CNT1 timer/counter clock when the CNT1 timer/counter
value is equal to the compare value in the cnt1_cmp_val register.
|
R
|
|
2
|
cnt1_exp: This bit is set on the next
CNT1 timer/counter clock when the CNT1 timer/counter
value is zero. It is set regardless of the value of the
CNT1 auto reload control.
|
R
|
|
0
|
tmr_exp: This bit is set on the next TMR
timer clock when the TMR timer value is zero. It is set
regardless of the value of the TMR auto reload
control.
|
R
|
11.11.30 tim.int_sts2
|
Address: 0xFDB8
|
Reset: 0x0000
|
Type: R
|
Input capture timer interrupt
status register.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
13
|
cap6_ovwr: A new trigger event occurred
on capture input 6 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val6 register.
|
R
|
|
12
|
cap6: A trigger event has occurred on
capture input 6.
The capture time is stored in the tim.cap_val6 register.
|
R
|
|
11
|
cap5_ovwr: A new trigger event occurred
on capture input 5 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val5 register.
|
R
|
|
10
|
cap5: A trigger event has occurred on
capture input 5.
The capture time is stored in the tim.cap_val5 register.
|
R
|
|
9
|
cap4_ovwr: A new trigger event occurred
on capture input 4 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val4 register.
|
R
|
|
8
|
cap4: A trigger event has occurred on
capture input 4.
The capture time is stored in the tim.cap_val4 register.
|
R
|
|
7
|
cap3_ovwr: A new trigger event occurred
on capture input 3 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val3 register.
|
R
|
|
6
|
cap3: A trigger event has occurred on
capture input 3.
The capture time is stored in the tim.cap_val3 register.
|
R
|
|
5
|
cap2_ovwr: A new trigger event occurred
on capture input 2 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val2 register.
|
R
|
|
4
|
cap2: A trigger event has occurred on
capture input 2.
The capture time is stored in the tim.cap_val2 register.
|
R
|
|
3
|
cap1_ovwr: A new trigger event occurred
on capture input 1 before the previous capture time
value was read.
The new capture time is stored in the tim.cap_val1 register.
|
R
|
|
2
|
cap1: A trigger event has occurred on
capture input 1.
The capture time is stored in the tim.cap_val1 register.
|
R
|
|
0
|
cap_exp: This bit is set if a count
strobe (capture timer clock edge) occurs when the
capture timer has reached its maximum value.
|
R
|
11.11.31 tim.int_en1
|
Address: 0xFDBA
|
Reset: 0x0000
|
Type: RW
|
Register tim.int_en1 enables the interrupt events
described in the tim.int_sts1
register. It forms a set/clear pair with the tim.int_dis1 register. Setting a bit to
'1' enables the interrupt for that bit. Reading this
register returns the current value of the interrupt enable
control for each bit.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
11
|
ltmr_exp: Enables the long interval
timer interrupt.
|
RW
|
|
10
|
wdog_exp: Enables the watchdog timer
interrupt.
|
RW
|
|
9
|
pwm2_match: Enables the PWM2 timer
transition match interrupt.
|
RW
|
|
8
|
pwm2_exp: Enables the PWM2 timer
interrupt.
|
RW
|
|
7
|
pwm1_match: Enables the PWM1 timer
transition match interrupt.
|
RW
|
|
6
|
pwm1_exp: Enables the PWM1 timer
interrupt.
|
RW
|
|
5
|
cnt2_match: Enables the CNT2
timer/counter compare interrupt.
|
RW
|
|
4
|
cnt2_exp: Enables the CNT2 timer/counter
interrupt.
|
RW
|
|
3
|
cnt1_match: Enables the CNT1
timer/counter compare interrupt.
|
RW
|
|
2
|
cnt1_exp: Enables the CNT1 timer/counter
interrupt.
|
RW
|
|
0
|
tmr_exp: Enables the TMR clock timer
interrupt.
|
RW
|
11.11.32 tim.int_en2
|
Address: 0xFDBC
|
Reset: 0x0000
|
Type: RW
|
Register tim.int_en2 enables the interrupt events
described in the tim.int_sts2
register. It forms a set/clear pair with the tim.int_dis2 register. Setting a bit to
'1' enables the interrupt for that bit. Reading this
register returns the current value of the interrupt enable
control for each bit.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
13
|
cap6_ovwr: Enables the input 6 capture
overwrite interrupt.
|
RW
|
|
12
|
cap6: Enables the input 6 capture
interrupt.
|
RW
|
|
11
|
cap5_ovwr: Enables the input 5 capture
overwrite interrupt.
|
RW
|
|
10
|
cap5: Enables the input 5 capture
interrupt.
|
RW
|
|
9
|
cap4_ovwr: Enables the input 4 capture
overwrite interrupt.
|
RW
|
|
8
|
cap4: Enables the input 4 capture
interrupt.
|
RW
|
|
7
|
cap3_ovwr: Enables the input 3 capture
overwrite interrupt.
|
RW
|
|
6
|
cap3: Enables the input 3 capture
interrupt.
|
RW
|
|
5
|
cap2_ovwr: Enables the input 2 capture
overwrite interrupt.
|
RW
|
|
4
|
cap2: Enables the input 2 capture
interrupt.
|
RW
|
|
3
|
cap1_ovwr: Enables the input 1 capture
overwrite interrupt.
|
RW
|
|
2
|
cap1: Enables the input 1 capture
interrupt.
|
RW
|
|
0
|
cap_exp: Enables the capture timer
overflow interrupt.
|
RW
|
11.11.33 tim.int_dis1
|
Address: 0xFDBE
|
Reset: 0x0000
|
Type: W
|
Register tim.int_dis1 disables the interrupt events
described in the tim.int_sts1
register. It forms a set/clear pair with the tim.int_en1 register. Setting a bit to
'1' disables the interrupt for that bit. If an
interrupt is disabled, no interrupt is generated for that
event, but the value of the interrupt status register is still
updated. Reading this register returns zero.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
11
|
ltmr_exp: Disables the long interval
timer interrupt.
|
W
|
|
10
|
wdog_exp: Disables the watchdog timer
interrupt.
|
W
|
|
9
|
pwm2_match: Disables the PWM2 timer
transition match interrupt.
|
W
|
|
8
|
pwm2_exp: Disables the PWM2 timer
interrupt.
|
W
|
|
7
|
pwm1_match: Disables the PWM1 timer
transition match interrupt.
|
W
|
|
6
|
pwm1_exp: Disables the PWM1 timer
interrupt.
|
W
|
|
5
|
cnt2_match: Disables the CNT2
timer/counter compare interrupt.
|
W
|
|
4
|
cnt2_exp: Disables the CNT2
timer/counter interrupt.
|
W
|
|
3
|
cnt1_match: Disables the CNT1
timer/counter compare interrupt.
|
W
|
|
2
|
cnt1_exp: Disables the CNT1
timer/counter interrupt.
|
W
|
|
0
|
tmr_exp: Disables the TMR clock timer
interrupt.
|
W
|
11.11.34 tim.int_dis2
|
Address: 0xFDC0
|
Reset: 0x0000
|
Type: W
|
Register tim.int_dis2 disables the interrupt events
described in the tim.int_sts2
register. It forms a set/clear pair with the tim.int_en2 register. Setting a bit to
'1' disables the interrupt for that bit. If an
interrupt is disabled, no interrupt is generated for that
event, but the value of the interrupt status register is still
updated. Reading this register returns zero.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
13
|
cap6_ovwr: Disables the input 6 capture
overwrite interrupt.
|
W
|
|
12
|
cap6: Disables the input 6 capture
interrupt.
|
W
|
|
11
|
cap5_ovwr: Disables the input 5 capture
overwrite interrupt.
|
W
|
|
10
|
cap5: Disables the input 5 capture
interrupt.
|
W
|
|
9
|
cap4_ovwr: Disables the input 4 capture
overwrite interrupt.
|
W
|
|
8
|
cap4: Disables the input 4 capture
interrupt.
|
W
|
|
7
|
cap3_ovwr: Disables the input 3 capture
overwrite interrupt.
|
W
|
|
6
|
cap3: Disables the input 3 capture
interrupt.
|
W
|
|
5
|
cap2_ovwr: Disables the input 2 capture
overwrite interrupt.
|
W
|
|
4
|
cap2: Disables the input 2 capture
interrupt.
|
W
|
|
3
|
cap1_ovwr: Disables the input 1 capture
overwrite interrupt.
|
W
|
|
2
|
cap1: Disables the input 1 capture
interrupt.
|
W
|
|
0
|
cap_exp: Disables the capture timer
overflow interrupt.
|
W
|
11.11.35 tim.int_clr1
|
Address: 0xFDC2
|
Reset: 0x0000
|
Type: W
|
Register tim.int_clr1 clears the interrupt events
described in the tim.int_sts1
register. Setting a bit to '1' clears the
corresponding bit in the status register.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
11
|
ltmr_exp: Clears the long interval timer
interrupt.
|
W
|
|
10
|
wdog_exp: Clears the watchdog timer
interrupt.
|
W
|
|
9
|
pwm2_match: Clears the PWM2 timer
transition match interrupt.
|
W
|
|
8
|
pwm2_exp: Clears the PWM2 timer
interrupt.
|
W
|
|
7
|
pwm1_match: Clears the PWM1 timer
transition match interrupt.
|
W
|
|
6
|
pwm1_exp: Clears the PWM1 timer
interrupt.
|
W
|
|
5
|
cnt2_match: Clears the CNT2
timer/counter compare interrupt.
|
W
|
|
4
|
cnt2_exp: Clears the CNT2 timer/counter
interrupt.
|
W
|
|
3
|
cnt1_match: Clears the CNT1
timer/counter compare interrupt.
|
W
|
|
2
|
cnt1_exp: Clears the CNT1 timer/counter
interrupt.
|
W
|
|
0
|
tmr_exp: Clears the TMR clock timer
interrupt.
|
W
|
11.11.36 tim.int_clr2
|
Address: 0xFDC4
|
Reset: 0x0000
|
Type: W
|
Register tim.int_clr2 clears the capture timer
overflow interrupt events described in the tim.int_sts2 register. Setting a bit to
'1' clears the corresponding bit in the status
register. The input capture interrupts are cleared
automatically when the corresponding capture value registers
are read.
The register contains the
following fields.
|
Bits
|
Field
|
Type
|
|
13
|
cap6_ovwr: Clears the input 6 capture
overwrite interrupt.
|
W
|
|
11
|
cap5_ovwr: Clears the input 5 capture
overwrite interrupt.
|
W
|
|
9
|
cap4_ovwr: Clears the input 4 capture
overwrite interrupt.
|
W
|
|
7
|
cap3_ovwr: Clears the input 3 capture
overwrite interrupt.
|
W
|
|
5
|
cap2_ovwr: Clears the input 2 capture
overwrite interrupt.
|
W
|
|
3
|
cap1_ovwr: Clears the input 1 capture
overwrite interrupt.
|
W
|
|
0
|
cap_exp: Clears the capture timer
overflow interrupt.
|
W
|
Contents
Previous Chapter
Next Chapter
