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10 Parallel I/O

eCOG1X contains both General Purpose I/O (GPIO) and Parallel I/O (PIO) peripherals. PIO allows users to control groups of 8 or 16 I/O signals at a time. GPIO provides users with signals that can be individually controlled.

PIO is typically used for bus signals where it is necessary for the whole bus to change simultaneously, for example driving a parallel word into a DAC. GPIO is typically used for controlling individual signals, for example the Output Enable of a DAC.

10.1 Overview

eCOG1X contains two 16-bit wide parallel I/O buses that can be routed to the chip level ports of the eCOG1X as described in Section 8, Port Configurator. The ports are named PIOA and PIOB. The signals within the port are named PIOA_0 to PIOA_15 and PIOB_0 to PIOB_15.

Figure 19: Parallel I/O peripheral module

Each PIO port can be individually configured as an input or output port. In addition, each port can be configured in a number of different modes:

The pio.cfg register is used to configure each PIO port individually. The *_op_mode bit field selects either open-drain or driven output mode, the *_pullup bit field enables or disables the internal pull-up resistor for the port, and the *_ip_en bit field is used to enable or disable the port input. If the input port is enabled, then the port input data register contains the current pin states. Disabling the input port function can reduce power consumption when the application does not need to read back the pin states. The internal pull-up resistors are available only when the PIO peripheral signals are routed to ports N, P, Q, R or S.

The pio.ctrl register individually controls the output enable for each PIO port. Two bits forming a set/clear pair are used for each port to enable and disable all the outputs of that port. Writing a '1' to the *_op_en field enables the output port; writing a '1' to the *_op_dis field disables the output port (Hi-Z). Writing '1' to both *_op_en and *_op_dis bit fields toggles the state of the internal output enable signal. Writing a '0' to either field has no effect.

10.2 Performance

The PIO ports have been implemented with input synchronisation and change detection circuitry, both to reduce the probability of erroneous values being propagated into the PIO input register and to simplify the software driver implementation.

When reading from a PIO input port, it is necessary to be aware of these features, since they add a delay between changes occurring on the external port pins and the change being visible to software via the pio.pa_in and pio.pb_in registers.

10.2.1 Delay Due to Input Synchronisation

The input synchroniser samples the external asynchronous signal and sychronises it to the local interface clock (if_clk). This introduces a delay time of between one and two peripheral if_clk clock cycles between the external PIO port pins and the input change detection circuitry,

Note the relationship between the input sychronisation delay and the frequency of the if_clk clock signal to the PIO ports. In order to achieve the lowest delay time between changes occurring on the external ports and the change being visible to the software in the pio.pa_in and pio.pb_in registers, it is necessary to set if_clk to its maximum frequency.

10.2.2 Delay Due to Input Change Detection

The PIO ports have an additional delay of three if_clk clock cycles between the input synchronisation circuitry (described above) and any input change being visible to software in the pio.pa_in and pio.pb_in registers. This delay can be longer if the value on the PIO port is not stable. This is due to the input change detection circuitry, which waits for the input value on each input port to be stable (the same 16-bit value) for three if_clk clock cycles. This reduces the probability of erroneous values being sampled. This also means that software does not have to perform this same debounce action, so that now it just has to read the pio.pa_in and pio.pb_in registers once and the value is known to be stable.

As for the input synchronisation delay, note the relationship between the change detection delay and the if_clk peripheral clock frequency. The overall delay between a change occurring on the external ports and it being visible to software in the pio.pa_in and pio.pb_in registers is typically 4 to 5 if_clk cycles, but can be significantly longer.

The if_clk frequency depends on the CPU clock frequency, set by the cpu_clk_div and prescaler bit fields in the ssm.cpu register. The if_clk frequency is equal to the CPU clock frequency divided by 2.

10.3 Parallel I/O Registers

The Parallel I/O peripheral block contains the following registers:

Table 34: Parallel I/O registers

Address

Name

Reset

Type

Page

0xFAB0

pio.cfg

0x0000

RW

10.3.1

0xFAB2

pio.ctrl

0x0000

RW

10.3.2

0xFAB4

pio.pa_out

0x0000

RW

10.3.3

0xFAB6

pio.pa_in

0x0000

R

10.3.4

0xFAB8

pio.pb_out

0x0000

RW

10.3.5

0xFABA

pio.pb_in

0x0000

R

10.3.6

10.3.1 pio.cfg

Address: 0xFAB0

Reset: 0x0000

Type: RW

This register configures the PIOA and PIOB parallel ports.

The register contains the following fields.

Bits

Field

Type

10

b_pullup: Writing a '1' to this bit enables internal pull-up resistors for all signals on port PIOB. Writing a '0' to this bit disables the pull-up resistors. The internal pull-up resistors are available only when the PIO peripheral signals are routed to ports N, P, Q, R or S.

RW

9

b_ip_en: Writing a '1' to this bit enables the port input function for PIOB. Writing a '0' to this bit disables the input function and can be used to reduce power consumption.
When the port input is enabled, reading the pio.pb_in register returns the current state of the pins on port PIOB.

RW

8

b_op_mode: Writing a '1' to this bit configures PIOB for open-drain outputs. Writing a '0' to this bit configures PIOB for normal outputs.

RW

2

a_pullup: Writing a '1' to this bit enables internal pull-up resistors for all signals on port PIOA. Writing a '0' to this bit disables the pull-up resistors. The internal pull-up resistors are available only when the PIO peripheral signals are routed to ports N, P, Q, R or S.

RW

1

a_ip_en: Writing a '1' to this bit enables the port input function for PIOA. Writing a '0' to this bit disables the input function and can be used to reduce power consumption.
When the port input is enabled, reading the pio.pa_in register returns the current state of the pins on port PIOA.

RW

0

a_op_mode: Writing a '1' to this bit configures PIOA for open-drain outputs. Writing a '0' to this bit configures PIOA for normal outputs.

RW

10.3.2 pio.ctrl

Address: 0xFAB2

Reset: 0x0000

Type: RW

This register controls the output enable for PIOA and PIOB.

The register contains the following fields.

Bits

Field

Type

9

b_op_dis: Writing a '1' to this bit disables the output of PIOB.
Reading this bit returns '0'.

RW

8

b_ op_en: Writing a '1' to this bit enables the output of PIOB.
Reading this bit returns the current output enable status of PIOB.
This bit forms a set/clear pair with b_op_dis. Writing a '1' to both bits toggles the internal output enable signal.

RW

1

a_ op_dis: Writing a '1' to this bit disables the output of PIOA.
Reading this bit returns '0'.

RW

0

a_ op_en: Writing a '1' to this bit enables the output of PIOA
Reading this bit returns the current output enable status of PIOA.
This bit forms a set/clear pair with a_op_dis. Writing a '1' to both bits toggles the internal output enable signal.

RW

10.3.3 pio.pa_out

Address: 0xFAB4

Reset: 0x0000

Type: RW

This register is used to write data to PIOA.

The register contains the following field.

Bits

Field

Type

15:0

pa_out: Writing to this register writes 16 bits of data to PIOA. A read from this register returns the last value written to this register, which may be different to the actual values at the pins. The value at the pins is read from pio.pa_in when the input port is enabled.

RW

10.3.4 pio.pa_in

Address: 0xFAB6

Reset: 0x0000

Type: R

This read only register contains the values at PIOA.

The register contains the following field.

Bits

Field

Type

15:0

pa_in: Reading this register returns the value of the signals at PIOA when the input port is enabled. If the PIO port is set for open drain outputs, this may be different from the last value written to the PIO output register pio.pa_out.

R

10.3.5 pio.pb_out

Address: 0xFAB8

Reset: 0x0000

Type: RW

This register is used to write data to PIOB.

The register contains the following field.

Bits

Field

Type

15:0

pb_out: Writing to this register writes 16 bits of data to PIOB. A read from this register returns the last value written to this register, which may be different to the actual values at the pins. The value at the pins is read from pio.pb_in when the input port is enabled.

RW

10.3.6 pio.pb_in

Address: 0xFABA

Reset: 0x0000

Type: R

This read only register contains the values at PIOB.

The register contains the following field.

Bits

Field

Type

15:0

pb_in: Reading this register returns the value of the signals at PIOB when the input port is enabled. If the PIO port is set for open drain outputs, this may be different from the last value written to the PIO output register pio.pb_out.

R

 

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