9 General Purpose I/O
eCOG1X contains both General
Purpose I/O (GPIO) and Parallel I/O (PIO) peripherals. PIO allows
users to control groups of 8 or 16 I/O signals at a time. GPIO
provides users with a set of signals that can be individually
controlled.
PIO is typically used for bus
signals where it is necessary for the whole bus to change
simultaneously, for example driving a parallel word into a DAC.
GPIO is typically used for controlling individual signals, for
example the Output Enable of a DAC.
9.1 Overview
eCOG1X contains a maximum of 120
General Purpose I/O signals, grouped into 19 ports named A to T.
Most ports are 8 bits wide, some are only 4 bits wide. The GPIO
signals are named according to the ports to which they are
connected, GPIOA_0-7 to GPIOT_0-3.
Each GPIO signal can be
individually configured as an input or output. When the GPIO
signal is configured as an output, the value driven onto the
pin can be read at the input register.
The GPIO signals are controlled
by bit fields in registers. Each set of 16-bit registers
controls a pair of I/O ports, with 8 bits for each port. Note
that ports C and D have only four bits for each port.
At reset, all interrupts are
disabled and all outputs are disabled. If a GPIO is enabled
following reset, it is driven low.
9.2 GPIO Inputs
The states of the GPIO pins are
read as inputs from the gpio.xy.ip_state registers, provided the port
input function is enabled by setting bits in the gpio.xy.ip_en registers. The port input
function can be disabled to reduce power consumption for unused
inputs. Disabled inputs are read back as zero from the gpio.xy.ip_state registers. All inputs are
synchronised to the internal if_clk clock signal, derived from the CPU
clock.
9.3 GPIO Outputs
For each GPIO signal, there are
two bit field registers that control whether the signal is
enabled or disabled. When the GPIO is enabled, the eCOG1X drives
a high or low signal onto the pin; when the GPIO is disabled,
the eCOG1X pin is in high impedance and acts as an input to
eCOG1X. These bits form set/clear pairs for the internal latched
output enable signals. Writing '1' to bits in the gpio.xy.op_en register enables the
corresponding outputs, where xy
represents the pair of ports controlled by the register; writing
'1' to bits in the gpio.xy.op_dis register disables the outputs.
Writing '0' to bits in these registers leaves the output
enable state unchanged. Users should not use a read-modify-write
technique to control these fields.
For each GPIO signal, there are
two bit field registers that control whether a GPIO configured
as an output is driven high or low. These fields also form
set/clear pairs for the latched output signals, similar to the
gpio.xy.op_en and gpio.xy.op_dis registers. Writing '1' to
bits in the gpio.xy.op_set register
sets the corresponding outputs high; writing '1' to bits in
the gpio.xy.op_clr register sets
the outputs low. Writing '0' to bits in these registers
leaves the output state unchanged. The internal state of a GPIO
output signal is preserved when the output is disabled.
The GPIOs can be configured as
open-drain signals, and on some ports an internal pull-up
resistor can be connected if required. Writing a '1' to bits
in the gpio.xy.op_mode register
configures the output as open-drain, '0' configures it as
normally driven. Writing a '1' to bits in the gpio.xy.pullup_en register connects the
internal pull-up resistor (if present on the selected port) to
the pin, and writing a '1' to bits in the gpio.xy.pullup_dis register disconnects the
internal pull-up resistor. The internal pull-up resistors are
implemented only on ports A, B, K, L, N, P, Q, R, S and T.
The GPIOs can be configured to
behave as open-source signals. This is achieved by permanently
setting the signals and enabling/disabling the output stage
manually. In this mode an external pull-down resistor is
necessary to prevent the pin floating when disabled. The table
below illustrates the use of the GPIO enable and disable to
control them as open-drain and open-source signals.
Table 31: Using GPIO as
open-drain or open-source
|
Signal
Properties
|
GPIO
Configuration
|
|
Mode
|
Resistor
|
Logic
Level
|
Signal
|
Output
|
|
open-drain
|
internal pull-up
|
1
|
clear
|
disabled
|
|
0
|
enabled
|
|
open-source
|
external pull-down
|
0
|
set
|
disabled
|
|
1
|
enabled
|
9.4 GPIO Configuration
All I/O ports can be configured
either for GPIO or for a peripheral function set by the port
configurator. The gpio.xy.op_sel
register controls which port pins are used for GPIO. Writing a
'1' to bit fields in this register selects the corresponding
port outputs for GPIO, overriding any peripheral signals
selected by the port configurator select registers. Writing a
'0' to bit fields in this register returns the port pin to
the peripheral function selected by the port configurator.
Note that the GPIO input function
is always available, even when the GPIO output function is
deselected and the port pin is controlled by another peripheral
function.
9.5 GPIO Interrupts
The GPIO signals may be
configured to generate edge or level triggered interrupts on a
high or low level, a rising, falling, or either edge on the
selected port pin. Edge triggered and level triggered interrupts
set the corresponding interrupt status bits in the gpio.xy.int_sts interrupt status registers
when the selected edge or level is detected. All GPIO signals
share the same interrupt vector. If multiple GPIO signals are
configured to generate an interrupt, the interrupt handler is
responsible for deciding which GPIO is the source of the
interrupt by reading the gpio.xy.int_sts registers.
When enabled, GPIO interrupts are
configured by bit fields in three registers, gpio.xy.cfg_edge1, gpio.xy.cfg_edge0 and gpio.xy.int_level. The combination of bit
fields in these three registers is used to select the interrupt
event. The bit field values are shown in the table below.
Table 32: GPIO interrupt
configuration
|
Register
|
Interrupt Function
|
|
cfg_edge1
|
cfg_edge0
|
int_level
|
|
0
|
0
|
0
|
low level
|
|
0
|
0
|
1
|
high level
|
|
0
|
1
|
X
|
falling edge
|
|
1
|
0
|
X
|
rising edge
|
|
1
|
1
|
X
|
any edge
|
GPIO interrupts are enabled by
writing a '1' to bit fields in the gpio.xy.int_en registers, and disabled by
writing a '1' to bit fields in the gpio.xy.int_dis registers. Interrupt status
is read from the gpio.xy.int_sts
registers, and interrupts are cleared by writing a '1' to
bit fields in the gpio.xy.int_clr
registers.
GPIO interrupts cause the
processor to wake up from sleep mode and begin executing
instructions at the interrupt handler for GPIO, unless input
wakeup events are disabled by setting the wakeon_if_dis bit field in the ssm.cfg register. The GPIO interrupt status
registers may be used to determine which pin caused the wakeup.
Sleep mode is discussed in Section 3.3, Processor Operating Modes.
9.6 Interfacing to 5V Logic
The eCOG1X has several 5V
tolerant GPIO pins, available on the following port signals:
PortB_0-4, PortK_0-3, PortL_0-3,
PortN_0-7, PortP_0-7, PortQ_0-7.
These must be tristated or in
open-drain mode when used with external 5V logic.
For inputs, the port pins are
tristated by writing a '1' to the appropriate bits in the
gpio.xy.op_dis register. The
external 5V signal may be connected directly to the input
pin.
For I/O operation, the port
pins must be used in open-drain mode with the internal pull-up
resistors disabled. This configuration is selected by writing
a '1' to the appropriate bits in the gpio.xy.mode and gpio.xy.pullup_dis registers. An external
pull-up resistor to the 5V supply is required.
The value of the external
pull-up resistor should be chosen to balance power consumption
against noise immunity. Typical values are 10kΩ to
22kΩ; it is recommended that the value is not less
than 2.7kΩ to keep the load current within the eCOG1X
output current sink capability. Care should be taken to keep
circuit board tracks short, especially for high speed signals
or high values of the pull-up resistor.
9.7 GPIO Register Bit
Fields
All the GPIO control registers
have similar bit fields. Each register has 16 bits controlling a
specific function for two ports, with 8 bits assigned to each
port. The low 8 bits control the lower lettered port, and the
high 8 bits control the higher lettered port.
The GPIO registers for 4-bit
ports such as C and D have only four bits for each port instead
of eight. Bits 0-3 control a 4-bit port in the lower half of the
register, and bits 8-11 control a 4-bit port in the higher
half.
9.8 GPIO Register Functions
As described above, each GPIO
register contains bit fields which provide full control over the
corresponding port inputs and outputs. Replace the characters
"xy" with the appropriate pair for the specific ports
as listed in the table in Section 9.9.
- gpio.xy.cfg_edge1
Writing a '1' to bits in this register enables edge-triggered
interrupts for rising edges on the selected signals. If the
corresponding bits in both the gpio.xy.cfg_edge1 and gpio.xy.cfg_edge0 registers are set to
'1', then interrupts are generated on both rising and falling
edges. If the corresponding bits in both these registers are set
to '0', then interrupts are level-triggered rather than
edge-triggered and the active level is set by the gpio.xy.int_level register.
- gpio.xy.cfg_edge0
Writing a '1' to bits in this register enables edge-triggered
interrupts for falling edges on the selected signals. If the
corresponding bits in both the gpio.xy.cfg_edge1 and gpio.xy.cfg_edge0 registers are set to
'1', then interrupts are generated on both rising and falling
edges. If the corresponding bits in both these registers are set
to '0', then interrupts are level-triggered rather than
edge-triggered and the active level is set by the gpio.xy.int_level register.
- gpio.xy.op_mode
Configures the port output mode.
'1' = open drain, '0' = driven.
- gpio.xy.op_sel
Selects the corresponding port outputs for GPIO,
overriding any peripheral signals selected by the port
configurator select registers.
'1' = GPIO, '0' = port configurator function.
- gpio.xy.ip_en
Writing a '1' to bits in this register enables
the input signal paths and synchronisers.
- gpio.xy.op_set
Writing a '1' to bits in this register sets the
port outputs to '1'.
Reading this register returns the current state of the output
port bits. Note that the actual pin state may be different if the
port pin is disabled or tristated.
- gpio.xy.op_clr
Writing a '1' to bits in this register sets the
port outputs to '0'.
- gpio.xy.op_en
Writing a '1' to bits in this register enables
the port outputs.
Reading this register returns the current state of the port
enable bits.
- gpio.xy.op_dis
Writing a '1' to bits in this register disables
the port outputs.
- gpio.xy.pullup_en
Writing a '1' to bits in this register enables
the on-chip pull-up resistors for the selected port pins. Reading
this register returns the current state of the pull-up enable
bits.
Note that the pull-up resistors are implemented only on ports A,
B, K, L, N, P, Q, R, S, T.
- gpio.xy.pullup_dis
Writing a '1' to bits in this register disables
the on-chip pull-up resistors for the selected port pins. Note
that the pull-up resistors are implemented only on ports A, B, K,
L, N, P, Q, R, S and T.
- gpio.xy.ip_state
Reading this register returns the current state of
the port input pins.
- gpio.xy.int_level
Selects whether level-triggered interrupts are
generated for a low or high level on the input signal.
Level-triggered interrupts are configured when the corresponding
bit fields in the gpio.xy.cfg_edge1
and gpio.xy.cfg_edge0 registers are
both set to '0'.
'1' = high level, '0' = low level.
- gpio.xy.int_en
Writing a '1' to bits in this register enables
interrupts.
Reading this register returns the current state of the interrupt
enable bits.
- gpio.xy.int_dis
Writing a '1' to bits in this register disables
interrupts.
- gpio.xy.int_clr
Writing a '1' to bits in this register clears
the interrupt status bits.
- gpio.xy.int_sts
Reading this register returns the interrupt status
bits.
9.9 GPIO Registers
The General Purpose I/O
peripheral block contains the following registers:
Table 33: General purpose I/O
registers
|
Address
|
Name
|
Reset
|
Type
|
|
0xFABC
|
gpio.ab.cfg_edge1
|
0x0000
|
RW
|
|
0xFABE
|
gpio.ab.cfg_edge0
|
0x0000
|
RW
|
|
0xFAC0
|
gpio.ab.op_mode
|
0x0000
|
RW
|
|
0xFAC2
|
gpio.ab.op_sel
|
0x0000
|
RW
|
|
0xFAC4
|
gpio.ab.ip_en
|
0x0000
|
RW
|
|
0xFAC6
|
gpio.ab.op_set
|
0x0000
|
RW
|
|
0xFAC8
|
gpio.ab.op_clr
|
0x0000
|
W
|
|
0xFACA
|
gpio.ab.op_en
|
0x0000
|
RW
|
|
0xFACC
|
gpio.ab.op_dis
|
0x0000
|
W
|
|
0xFACE
|
gpio.ab.pullup_en
|
0x0000
|
RW
|
|
0xFAD0
|
gpio.ab.pullup_dis
|
0x0000
|
W
|
|
0xFAD2
|
gpio.ab.ip_state
|
0x0000
|
R
|
|
0xFAD4
|
gpio.ab.int_level
|
0x0000
|
RW
|
|
0xFAD6
|
gpio.ab.int_en
|
0x0000
|
RW
|
|
0xFAD8
|
gpio.ab.int_dis
|
0x0000
|
W
|
|
0xFADA
|
gpio.ab.int_clr
|
0x0000
|
W
|
|
0xFADC
|
gpio.ab.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFADE
|
gpio.cd.cfg_edge1
|
0x0000
|
RW
|
|
0xFAE0
|
gpio.cd.cfg_edge0
|
0x0000
|
RW
|
|
0xFAE2
|
gpio.cd.op_mode
|
0x0000
|
RW
|
|
0xFAE4
|
gpio.cd.op_sel
|
0x0000
|
RW
|
|
0xFAE6
|
gpio.cd.ip_en
|
0x0000
|
RW
|
|
0xFAE8
|
gpio.cd.op_set
|
0x0000
|
RW
|
|
0xFAEA
|
gpio.cd.op_clr
|
0x0000
|
W
|
|
0xFAEC
|
gpio.cd.op_en
|
0x0000
|
RW
|
|
0xFAEE
|
gpio.cd.op_dis
|
0x0000
|
W
|
|
0xFAF0
|
gpio.cd.pullup_en
|
0x0000
|
RW
|
|
0xFAF2
|
gpio.cd.pullup_dis
|
0x0000
|
W
|
|
0xFAF4
|
gpio.cd.ip_state
|
0x0000
|
R
|
|
0xFAF6
|
gpio.cd.int_level
|
0x0000
|
RW
|
|
0xFAF8
|
gpio.cd.int_en
|
0x0000
|
RW
|
|
0xFAFA
|
gpio.cd.int_dis
|
0x0000
|
W
|
|
0xFAFC
|
gpio.cd.int_clr
|
0x0000
|
W
|
|
0xFAFE
|
gpio.cd.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFB00
|
gpio.ef.cfg_edge1
|
0x0000
|
RW
|
|
0xFB02
|
gpio.ef.cfg_edge0
|
0x0000
|
RW
|
|
0xFB04
|
gpio.ef.op_mode
|
0x0000
|
RW
|
|
0xFB06
|
gpio.ef.op_sel
|
0x0000
|
RW
|
|
0xFB08
|
gpio.ef.ip_en
|
0x0000
|
RW
|
|
0xFB0A
|
gpio.ef.op_set
|
0x0000
|
RW
|
|
0xFB0C
|
gpio.ef.op_clr
|
0x0000
|
W
|
|
0xFB0E
|
gpio.ef.op_en
|
0x0000
|
RW
|
|
0xFB10
|
gpio.ef.op_dis
|
0x0000
|
W
|
|
0xFB12
|
gpio.ef.pullup_en
|
0x0000
|
RW
|
|
0xFB14
|
gpio.ef.pullup_dis
|
0x0000
|
W
|
|
0xFB16
|
gpio.ef.ip_state
|
0x0000
|
R
|
|
0xFB18
|
gpio.ef.int_level
|
0x0000
|
RW
|
|
0xFB1A
|
gpio.ef.int_en
|
0x0000
|
RW
|
|
0xFB1C
|
gpio.ef.int_dis
|
0x0000
|
W
|
|
0xFB1E
|
gpio.ef.int_clr
|
0x0000
|
W
|
|
0xFB20
|
gpio.ef.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFB22
|
gpio.gh.cfg_edge1
|
0x0000
|
RW
|
|
0xFB24
|
gpio.gh.cfg_edge0
|
0x0000
|
RW
|
|
0xFB26
|
gpio.gh.op_mode
|
0x0000
|
RW
|
|
0xFB28
|
gpio.gh.op_sel
|
0x0000
|
RW
|
|
0xFB2A
|
gpio.gh.ip_en
|
0x0000
|
RW
|
|
0xFB2C
|
gpio.gh.op_set
|
0x0000
|
RW
|
|
0xFB2E
|
gpio.gh.op_clr
|
0x0000
|
W
|
|
0xFB30
|
gpio.gh.op_en
|
0x0000
|
RW
|
|
0xFB32
|
gpio.gh.op_dis
|
0x0000
|
W
|
|
0xFB34
|
gpio.gh.pullup_en
|
0x0000
|
RW
|
|
0xFB36
|
gpio.gh.pullup_dis
|
0x0000
|
W
|
|
0xFB38
|
gpio.gh.ip_state
|
0x0000
|
R
|
|
0xFB3A
|
gpio.gh.int_level
|
0x0000
|
RW
|
|
0xFB3C
|
gpio.gh.int_en
|
0x0000
|
RW
|
|
0xFB3E
|
gpio.gh.int_dis
|
0x0000
|
W
|
|
0xFB40
|
gpio.gh.int_clr
|
0x0000
|
W
|
|
0xFB42
|
gpio.gh.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFB44
|
gpio.ij.cfg_edge1
|
0x0000
|
RW
|
|
0xFB46
|
gpio.ij.cfg_edge0
|
0x0000
|
RW
|
|
0xFB48
|
gpio.ij.op_mode
|
0x0000
|
RW
|
|
0xFB4A
|
gpio.ij.op_sel
|
0x0000
|
RW
|
|
0xFB4C
|
gpio.ij.ip_en
|
0x0000
|
RW
|
|
0xFB4E
|
gpio.ij.op_set
|
0x0000
|
RW
|
|
0xFB50
|
gpio.ij.op_clr
|
0x0000
|
W
|
|
0xFB52
|
gpio.ij.op_en
|
0x0000
|
RW
|
|
0xFB54
|
gpio.ij.op_dis
|
0x0000
|
W
|
|
0xFB56
|
gpio.ij.pullup_en
|
0x0000
|
RW
|
|
0xFB58
|
gpio.ij.pullup_dis
|
0x0000
|
W
|
|
0xFB5A
|
gpio.ij.ip_state
|
0x0000
|
R
|
|
0xFB5C
|
gpio.ij.int_level
|
0x0000
|
RW
|
|
0xFB5E
|
gpio.ij.int_en
|
0x0000
|
RW
|
|
0xFB60
|
gpio.ij.int_dis
|
0x0000
|
W
|
|
0xFB62
|
gpio.ij.int_clr
|
0x0000
|
W
|
|
0xFB64
|
gpio.ij.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFB66
|
gpio.kl.cfg_edge1
|
0x0000
|
RW
|
|
0xFB68
|
gpio.kl.cfg_edge0
|
0x0000
|
RW
|
|
0xFB6A
|
gpio.kl.op_mode
|
0x0000
|
RW
|
|
0xFB6C
|
gpio.kl.op_sel
|
0x0000
|
RW
|
|
0xFB6E
|
gpio.kl.ip_en
|
0x0000
|
RW
|
|
0xFB70
|
gpio.kl.op_set
|
0x0000
|
RW
|
|
0xFB72
|
gpio.kl.op_clr
|
0x0000
|
W
|
|
0xFB74
|
gpio.kl.op_en
|
0x0000
|
RW
|
|
0xFB76
|
gpio.kl.op_dis
|
0x0000
|
W
|
|
0xFB78
|
gpio.kl.pullup_en
|
0x0000
|
RW
|
|
0xFB7A
|
gpio.kl.pullup_dis
|
0x0000
|
W
|
|
0xFB7C
|
gpio.kl.ip_state
|
0x0000
|
R
|
|
0xFB7E
|
gpio.kl.int_level
|
0x0000
|
RW
|
|
0xFB80
|
gpio.kl.int_en
|
0x0000
|
RW
|
|
0xFB82
|
gpio.kl.int_dis
|
0x0000
|
W
|
|
0xFB84
|
gpio.kl.int_clr
|
0x0000
|
W
|
|
0xFB86
|
gpio.kl.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFB88
|
gpio.mn.cfg_edge1
|
0x0000
|
RW
|
|
0xFB8A
|
gpio.mn.cfg_edge0
|
0x0000
|
RW
|
|
0xFB8C
|
gpio.mn.op_mode
|
0x0000
|
RW
|
|
0xFB8E
|
gpio.mn.op_sel
|
0x0000
|
RW
|
|
0xFB90
|
gpio.mn.ip_en
|
0x0000
|
RW
|
|
0xFB92
|
gpio.mn.op_set
|
0x0000
|
RW
|
|
0xFB94
|
gpio.mn.op_clr
|
0x0000
|
W
|
|
0xFB96
|
gpio.mn.op_en
|
0x0000
|
RW
|
|
0xFB98
|
gpio.mn.op_dis
|
0x0000
|
W
|
|
0xFB9A
|
gpio.mn.pullup_en
|
0x0000
|
RW
|
|
0xFB9C
|
gpio.mn.pullup_dis
|
0x0000
|
W
|
|
0xFB9E
|
gpio.mn.ip_state
|
0x0000
|
R
|
|
0xFBA0
|
gpio.mn.int_level
|
0x0000
|
RW
|
|
0xFBA2
|
gpio.mn.int_en
|
0x0000
|
RW
|
|
0xFBA4
|
gpio.mn.int_dis
|
0x0000
|
W
|
|
0xFBA6
|
gpio.mn.int_clr
|
0x0000
|
W
|
|
0xFBA8
|
gpio.mn.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFBAA
|
gpio.pq.cfg_edge1
|
0x0000
|
RW
|
|
0xFBAC
|
gpio.pq.cfg_edge0
|
0x0000
|
RW
|
|
0xFBAE
|
gpio.pq.op_mode
|
0x0000
|
RW
|
|
0xFBB0
|
gpio.pq.op_sel
|
0x0000
|
RW
|
|
0xFBB2
|
gpio.pq.ip_en
|
0x0000
|
RW
|
|
0xFBB4
|
gpio.pq.op_set
|
0x0000
|
RW
|
|
0xFBB6
|
gpio.pq.op_clr
|
0x0000
|
W
|
|
0xFBB8
|
gpio.pq.op_en
|
0x0000
|
RW
|
|
0xFBBA
|
gpio.pq.op_dis
|
0x0000
|
W
|
|
0xFBBC
|
gpio.pq.pullup_en
|
0x0000
|
RW
|
|
0xFBBE
|
gpio.pq.pullup_dis
|
0x0000
|
W
|
|
0xFBC0
|
gpio.pq.ip_state
|
0x0000
|
R
|
|
0xFBC2
|
gpio.pq.int_level
|
0x0000
|
RW
|
|
0xFBC4
|
gpio.pq.int_en
|
0x0000
|
RW
|
|
0xFBC6
|
gpio.pq.int_dis
|
0x0000
|
W
|
|
0xFBC8
|
gpio.pq.int_clr
|
0x0000
|
W
|
|
0xFBCA
|
gpio.pq.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFBCC
|
gpio.rs.cfg_edge1
|
0x0000
|
RW
|
|
0xFBCE
|
gpio.rs.cfg_edge0
|
0x0000
|
RW
|
|
0xFBD0
|
gpio.rs.op_mode
|
0x0000
|
RW
|
|
0xFBD2
|
gpio.rs.op_sel
|
0x0000
|
RW
|
|
0xFBD4
|
gpio.rs.ip_en
|
0x0000
|
RW
|
|
0xFBD6
|
gpio.rs.op_set
|
0x0000
|
RW
|
|
0xFBD8
|
gpio.rs.op_clr
|
0x0000
|
W
|
|
0xFBDA
|
gpio.rs.op_en
|
0x0000
|
RW
|
|
0xFBDC
|
gpio.rs.op_dis
|
0x0000
|
W
|
|
0xFBDE
|
gpio.rs.pullup_en
|
0x0000
|
RW
|
|
0xFBE0
|
gpio.rs.pullup_dis
|
0x0000
|
W
|
|
0xFBE2
|
gpio.rs.ip_state
|
0x0000
|
R
|
|
0xFBE4
|
gpio.rs.int_level
|
0x0000
|
RW
|
|
0xFBE6
|
gpio.rs.int_en
|
0x0000
|
RW
|
|
0xFBE8
|
gpio.rs.int_dis
|
0x0000
|
W
|
|
0xFBEA
|
gpio.rs.int_clr
|
0x0000
|
W
|
|
0xFBEC
|
gpio.rs.int_sts
|
0x0000
|
R
|
|
|
|
|
|
|
0xFBEE
|
gpio.t.cfg_edge1
|
0x0000
|
RW
|
|
0xFBF0
|
gpio.t.cfg_edge0
|
0x0000
|
RW
|
|
0xFBF2
|
gpio.t.op_mode
|
0x0000
|
RW
|
|
0xFBF4
|
gpio.t.op_sel
|
0x0000
|
RW
|
|
0xFBF6
|
gpio.t.ip_en
|
0x0000
|
RW
|
|
0xFBF8
|
gpio.t.op_set
|
0x0000
|
RW
|
|
0xFBFA
|
gpio.t.op_clr
|
0x0000
|
W
|
|
0xFBFC
|
gpio.t.op_en
|
0x0000
|
RW
|
|
0xFBFE
|
gpio.t.op_dis
|
0x0000
|
W
|
|
0xFC00
|
gpio.t.pullup_en
|
0x0000
|
RW
|
|
0xFC02
|
gpio.t.pullup_dis
|
0x0000
|
W
|
|
0xFC04
|
gpio.t.ip_state
|
0x0000
|
R
|
|
0xFC06
|
gpio.t.int_level
|
0x0000
|
RW
|
|
0xFC08
|
gpio.t.int_en
|
0x0000
|
RW
|
|
0xFC0A
|
gpio.t.int_dis
|
0x0000
|
W
|
|
0xFC0C
|
gpio.t.int_clr
|
0x0000
|
W
|
|
0xFC0E
|
gpio.t.int_sts
|
0x0000
|
R
|
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