Contents
1 Introduction
1.1 Additional Documents
1.2 Typographical Conventions
1.3 Part Identification
1.4 Glossary
1.5 Registers and Bit Fields
1.6 Disclaimer
2 Overview
2.1 eCOG1X Block Diagram
2.2 Feature List
2.3 eCOG1X Options
2.4 Pin Functions
2.5 CPU
2.6 Memory
2.7 Interrupts
2.8 Serial Peripherals
2.9 Timers
2.10 Port Configurator
2.11 External Host Interface
2.12 Analogue Voltage and Temperature
Sensors
2.13 eICE Debugger
2.14 Recommended Approach for This Document
3 CPU
3.1 Programmer's Model
3.2 Instruction Set
3.3 Processor Operating Modes
3.4 Flags
3.5 Instruction Formats
3.6 Instruction Timings
4 Memory Management Unit
4.1 Operation
4.2 Configuration
4.3 Internal RAM Organisation
4.4 Memory Management Unit Registers
5 Instruction Cache
5.1 Overview
5.2 Operation
5.3 Initialisation
5.4 Cache Tag Format
5.5 Cache Locking
5.6 Software Debugging with the Cache
5.7 Limitations
5.8 Instruction Cache Control Registers
6 Interrupts
6.1 Overview
6.2 Interrupt Handler
6.3 Interrupt Latency
6.4 Interrupt Priority
6.5 Interrupt Vectors
6.6 Timer Interrupts
6.7 DUSART Interrupts
6.8 User Serial Port Interrupts
6.9 Smart Card Interface Interrupts
6.10 IFR Interrupts
6.11 UART Interrupts
6.12 SPI Interrupts
6.13 I2C Interrupts
6.14 DUART Interrupts
6.15 External Host Interface Interrupts
7 System Support Module
7.1 System Clock Control
7.2 PLL and VCO Frequencies
7.3 Peripheral Clock Frequency Limits
7.4 Sleep
7.5 Deep Sleep
7.6 Wakeup
7.7 System Reset Control
7.8 Reset summary
7.9 System Support Module Registers
8 Port Configurator
8.1 Configuration Rules
8.2 Low Power Considerations
8.3 Port Configurator Registers
9 General Purpose I/O
9.1 Overview
9.2 GPIO Inputs
9.3 GPIO Outputs
9.4 GPIO Configuration
9.5 GPIO Interrupts
9.6 Interfacing to 5V Logic
9.7 GPIO Register Bit Fields
9.8 GPIO Register Functions
9.9 GPIO Registers
10 Parallel I/O
10.1 Overview
10.2 Performance
10.3 Parallel I/O Registers
11 Timer/Counter Module
11.1 Initialisation
11.2 Interrupts
11.3 Reload
11.4 Reading the Timer Count Registers
11.5 Timer
11.6 Counter
11.7 PWM
11.8 Capture Timer
11.9 Watchdog Timer
11.10 Long Interval Timer
11.11 Timer/Counter Registers
12 DUARTs
12.1 Initialisation
12.2 Receive Sampling
12.3 Transmit Sampling
12.4 Baud Rates
12.5 Transmitter
12.6 Receiver
12.7 DUART Registers
12.8 DUART1 Registers
12.9 DUART2 Registers
13 DUSART
13.1 Configuration
13.2 Initialisation
13.3 Receive Filter
13.4 Sample Strobe and Synchroniser
13.5 Parity Calculator
13.6 Transmit Serialiser
13.7 Protocol Control Engines
13.8 DUSART Registers
14 DUSART: I2C Serial Interface
14.1 Overview
14.2 Initialisation
14.3 Interrupts
14.4 I2C Control
14.5 I2C Master
14.6 I2C Slave
14.7 Arbitration
14.8 Limitations
14.9 I2C Registers
15 DUSART: SPI Serial Interface
15.1 Overview
15.2 Clock Initialisation
15.3 Serial Clock Polarity and Phase
15.4 SPI Controller
15.5 Chip Selects
15.6 Operation
15.7 Limitations
15.8 SPI Registers
16 DUSART: UART Serial Port
16.1 Overview
16.2 Initialisation
16.3 Baud rates
16.4 UART Serial Controller
16.5 Operation
16.6 UART Registers
17 DUSART: Smart Card Interface
17.1 Overview
17.2 SCI Control Finite State Machine
17.3 SCI Delay Timer
17.4 General Information
17.5 Smart Card Interface Registers
18 DUSART: Infra-Red Interface
18.1 Overview
18.2 Initialisation
18.3 Operation
18.4 IFR Counters
18.5 IFR Datapath
18.6 Infra-Red Interface Registers
19 DUSART: User Serial Port
19.1 Overview
19.2 Initialisation
19.3 Baud Rates
19.4 Design Description
19.5 USR Additional Functions
19.6 Example Frame Transmit and Receive
Sequences
19.7 User Serial Port Registers
20 External Memory Interface
20.1 External Signals
20.2 Bus Interface Mode
20.3 Bus Mode Connections
20.4 Bus Mode Timing Parameters
20.5 Bus Mode Timing Diagrams
20.6 SDRAM Interface Mode
20.7 SDRAM Connections
20.8 SDRAM Timing Parameters
20.9 SDRAM Timing Diagrams
20.10 SDRAM Mode Limitations
20.11 Address Error Interrupt
20.12 External Memory Interface Registers
21 External Host Interface
21.1 Memory Mapped Peripheral (MMP) Port
21.2 Direct Memory Access (DMA) Port
21.3 Access Arbitration
21.4 External Connections and Timing
21.5 External Host Interface Registers
22 Embedded Flash Memory
22.1 Overview
22.2 Reset Condition
22.3 Wait States
22.4 Programming
22.5 Write Protection
22.6 Erase Methods
22.7 Programming Methods
22.8 Device ID
22.9 Status Monitoring
22.10 Command Sequences
22.11 MMU Setup for Flash Memory Access
22.12 Operation Timings
22.13 Low Power Modes
22.14 Flash Timer
22.15 Flash Mode Changes
22.16 Flash Operation in Slow Mode
22.17 Changing from Fast to Slow Mode
22.18 Changing from Slow to Fast Mode
22.19 Embedded Flash Memory Registers
23 Analogue Functions
23.1 ADC
23.2 DAC
23.3 Voltage Reference
23.4 Power On Reset
23.5 Low Voltage Sensor
23.6 Temperature sensor
23.7 Supply Voltage Sensor
23.8 Analogue Multiplexer
23.9 Resolution and Scaling
23.10 ADC Output Data
23.11 ADC Conversion Modes
23.12 DAC Conversion Modes
23.13 Analogue Control Interface Registers
24 ESPI
24.1 Features
24.2 Overview
24.3 Clock Initialisation
24.4 Serial Clock Polarity and Phase
24.5 Chip Selects
24.6 Programmable Time Delays
24.7 Operation
24.8 Limitations
24.9 ESPI Registers
25 I2S
25.1 Overview
25.2 Features
25.3 Clock Initialisation
25.4 Operation
25.5 I2S Registers
26 LCD Controller
26.1 Features
26.2 Principles of Operation
26.3 LCD Controller Registers
27 MCPWM
27.1 Features
27.2 Controlling Electric Motors
27.3 Operation
27.4 MCPWM Registers
28 Dual Smart Card Interface
28.1 Features
28.2 Overview
28.3 Clock Generation
28.4 Activation and Deactivation Sequencing
28.5 Peripheral Clock Wakeup
28.6 Data Transmission and Reception
28.7 Receiver Operation
28.8 Transmitter Operation
28.9 Example Clock Configuration for EMV ATR
28.10 Dual Smart Card Interface Registers
29 Ethernet MAC
29.1 Overview
29.2 System Configuration
29.3 Buffers and Buffer Descriptors
29.4 Transmit Buffer Descriptor
29.5 Receive Buffer Descriptor
29.6 MAC Setup Buffer
29.7 EMAC Registers
Appendix A eCOG1X Options
A.1 eCOG1X0A5
A.2 eCOG1X1A5
A.3 eCOG1X4A5
A.4 eCOG1X5A5
A.5 eCOG1X8A5
A.6 eCOG1X9A5
A.7 eCOG1X10B5
A.8 eCOG1X14B5
A.9 eCOG1X10Z5
A.10 eCOG1X14Z5
Appendix B Applications Information
B.1 Connections
B.2 Power Supplies and Decoupling
Appendix C Electrical Characteristics
C.1 Recommended Operating Conditions
C.2 Absolute Maximum Ratings
C.3 Supply Current
C.4 DC Electrical Characteristics
C.5 AC Electrical Characteristics
C.6 Peripheral Clock Frequency Limits
C.7 Embedded Flash Memory Characteristics
C.8 Analogue Characteristics
Appendix D Mechanical Package Drawings
D.1 68QFN
D.2 100QFN
D.3 208BGA
Appendix E Circuit Board Pad Layout Drawings
E.1 68QFN
E.2 100QFN
E.3 208BGA
Appendix F eICE Debug Interface
F.1 Signal Functions
F.2 Handshake
F.3 Abort
F.4 eICE Command and Data Shift
F.5 Clocking and Initial Operation
F.6 eICE_LOADB and Reset
F.7 eICE Registers
F.8 eICE Commands
Appendix G Register Map
Appendix H Interrupt Vectors
Appendix I Port Select Options
I.1 Port A
I.2 Port B
I.3 Port C
I.4 Port D
I.5 Port E
I.6 Port F
I.7 Port G
I.8 Port H
I.9 Port I
I.10 Port J
I.11 Port K
I.12 Port L
I.13 Port M
I.14 Port N
I.15 Port P
I.16 Port Q
I.17 Port R
I.18 Port S
I.19 Port T
Appendix J Peripheral Routing Options
J.1 GPIO
J.2 PIO
J.3 DUART
J.4 DUSART
J.5 Timers
J.6 External Memory Interface (EMI)
J.7 External Host Interface (EHI)
J.8 USB Interface
J.9 Ethernet MAC
J.10 ESPI
J.11 I2S
J.12 LCD Controller
J.13 Motor Control PWM
J.14 Dual Smart Card Interface (DSCI)
J.15 Analogue I/O
Appendix K External Peripheral Signals
K.1 GPIO
K.2 PIO
K.3 DUART
K.4 DUSART
K.5 Timers
K.6 External Memory Interface
K.7 External Host Interface
K.8 USB Interface
K.9 Ethernet MAC
K.10 ESPI
K.11 I2S
K.12 LCD Controller
K.13 Motor Control PWM
K.14 Dual Smart Card Interface
Appendix L Contact Information
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